LTC3556
32
3556f
APPLICATIONS INFORMATION
USB Inrush Limiting
When a USB cable is plugged into a portable product,
the inductance of the cable and the high-Q ceramic input
capacitor form an L-C resonant circuit. If the cable does
not have adequate mutual coupling or if there is not much
impedance in the cable, it is possible for the voltage at
the input of the product to reach as high as twice the USB
voltage (~10V) before it settles out. To prevent excessive
voltage from damaging the LTC3556 during a hot insertion,
it is best to have a low voltage coefficient capacitor at the
V
BUS
pin to the LTC3556. This is achievable by selecting an
MLCC capacitor that has a higher voltage rating than that
required for the application. For example, a 16V, X5R, 10µF
capacitor in a 1206 case would be a more conservative
choice than a 6.3V, X5R, 10µF capacitor in a smaller 0805
case. The size of the input overshoot will be determined
by the “Q” of the resonant tank circuit formed by C
IN
and
the input lead inductance. It is recommended to measure
the input ringing with the selected components to verify
compliance with the Absolute Maximum specifi cations.
Alternatively, the following soft connect circuit (Figure 8)
can be employed. In this circuit, capacitor C1 holds MP1
off when the cable is first connected. Eventually C1 begins
to charge up to the USB input voltage applying increasing
gate support to MP1. The long time constant of R1 and
C1 prevent the current from building up in the cable too
fast thus dampening out any resonant overshoot.
Printed Circuit Board Layout Considerations
In order to be able to deliver maximum current under
all conditions, it is critical that the Exposed Pad on the
backside of the LTC3556 package be soldered to the PC
board ground. Failure to make thermal contact between
the Exposed Pad on the backside of the package and the
copper board will result in higher thermal resistances.
Furthermore, due to its high frequency switching circuitry,
it is imperative that the input capacitors, inductors and
output capacitors be as close to the LTC3556 as possible
and that there be an unbroken ground plane under the
LTC3556 and all of its external high frequency compo-
nents. High frequency currents such as the V
BUS
, V
IN1
,
V
IN2
and V
IN3
currents on the LTC3556, tend to find their
way along the ground plane in a myriad of paths ranging
from directly back to a mirror path beneath the incident
path on the top of the board. If there are slits or cuts
in the ground plane due to other traces on that layer,
the current will be forced to go around the slits. If high
frequency currents are not allowed to flow back through
their natural least-area path, excessive voltage will build
up and radiated emissions will occur. There should be a
group of vias under the grounded backside of the pack-
age leading directly down to an internal ground plane. To
minimize parasitic inductance, the ground plane should
be on the second layer of the PC board.
R1
40k
5V USB
INPUT
3556 F08
C1
100nF
C2
10µF
MP1
Si2333
USB CABLE
V
BUS
GND
LTC3556
Figure 8. USB Soft Connect Circuit
