10
Detailed Description
The HI1175 is a 2-step A/D converter featuring a 4-bit upper
comparator group and two lower comparator groups of 4 bits
each. The reference voltage can be obtained from the
onboard bias generator or be supplied externally. This IC
uses an offset canceling type comparator that operates
synchronously with an external clock. The operating modes of
the part are input sampling (S), hold (H), and compare (C).
The operation of the part is illustrated in Figure 2. A
reference voltage that is between V
RT
-V
RB
is constantly
applied to the upper 4-bit comparator group. V
I
(1) is
sampled with the falling edge of the first clock by the upper
comparator block. The lower block A also samples V
I
(1) on
the same edge. The upper comparator block finalizes
comparison data MD(1) with the rising edge of the first clock.
Simultaneously the reference supply generates a reference
voltage RV(1) that corresponds to the upper results and
applies it to the lower comparator block A. The lower
comparator block finalizes comparison data LD(1) with the
rising edge of the second clock. MD(1) and LD(1) are
combined and output as OUT(1) with the rising edge of the
third clock. There is a 2.5 cycle clock delay from the analog
input sampling point to the corresponding digital output data.
Notice how the lower comparator blocks A and B alternate
generating the lower data in order to increase the overall A/D
sampling rate.
Power, Grounding, and Decoupling
To reduce noise effects, separate the analog and digital
grounds.
In order to avoid latchup at power up, it is necessary that
AV
DD
and DV
DD
be driven from the same supply.
Bypass both the digital and analog V
DD
pins to their
respective grounds with a ceramic 0.1µF capacitor close to
the pin.
Analog Input
The input capacitance is small when compared with other
flash type A/D converters. However, it is necessary to drive
the input with an amplifier with sufficient bandwidth and drive
capability. In order to prevent parasitic oscillation, it may be
necessary to insert a low value (i.e., 0.24) resistor between
the output of the amplifier and the A/D input.
Reference Input
The range of the A/D is set by the voltage between V
RT
and
V
RB
. The internal bias generator will set V
RTS
to 2.6V and
V
RBS
to 0.6V. These can be used as the part reference by
shorting V
RT
and V
RTS
and V
RB
to V
RBS
. The analog input
range of the A/D will now be from 0.6V to 2.6V and is
referred to as Self Bias Mode 1. Self Bias Mode 2 is where
V
RB
is connected to AGND and V
RT
is shorted to V
RTS
.
The analog input range will now be from 0V to 2.4V.
Test Circuits
FIGURE 21. INTEGRAL AND DIFFERENTIAL NON-LINEARITY ERROR AND OFFSET VOLTAGE TEST CIRCUIT
-
V
IN
HI1175
DUT
8
CLK (20MHz)
+
A<B A>B
COMPARATOR
A8
A1
A0
B8
B1
B0
“0” “1”
8
S1
S2
-V
+V
S1 : ON IF A < B
S2 : ON IF A > B
BUFFER
DVM
CONTROLLER
8
TO
111 • • • 10
000 • • • 00
TO
TO
HI1175
11
FIGURE 22. MAXIMUM OPERATIONAL SPEED AND DIFFERENTIAL GAIN AND PHASE ERROR TEST CIRCUIT
FIGURE 23. DIGITAL OUTPUT CURRENT TEST CIRCUIT
HA5020 (Single)
HA5022(Dual)
HA5024 (Quad)
HA5013 (Triple)
HI1175 (8-Bit) HSP9501
HSP48901
HSP43881
HSP43168
HI3338 (8-Bit)
HI1171 (8-Bit)
HA5020 (Single)
HSP9501: Programmable Data Buffer
HSP48901: 3 x 3 Image Filter, 30MHz, 8-Bit
HSP43881: Digital Filter, 30MHz, 1-D and 2-D FIR Filters
HSP43168: Dual FIR Filter, 10-Bit, 33MHz/45MHz
CMOS Logic Available in HC, HCT, AC, ACT and FCT.
HA5013: Triple, 125MHz, I
OUT
= 20mA
HA5020: Single, 100MHz, I
OUT
= 30mA, Output Enable/Disable
HA5022: Dual, 125MHz, I
OUT
= 20mA, Output Enable/Disable
HA5024: Quad, 125MHz, I
OUT
= 20mA, Output Enable/Disable
FIGURE 24. 8-BIT SYSTEM COMPONENTS
Test Circuits (Continued)
SIGNAL
SOURCE
NTSC
SG
V
IN
8
8
SCOPE
VECTOR
620
DG
ERROR RATE
SG
(CW)
AMP
HI1175
DUT
ECL
TTL
D/A
10-BIT
-5.2V
CLK
1
2
1
2
HPF COUNTER
DP
620
-5.2V
ECL
TTL
f
C
-40
0
100
IRE
SYNC
BURST
0.6V
2.6V
40 IRE
MODULATION
0.6V
2.6V
f
C
-1kHz
HI20201
V
RT
V
IN
V
RB
CLK
OE
GND
V
DD
0.6V
2.6V
V
OL
I
OL
+
-
V
RT
V
IN
V
RB
CLK
OE
GND
V
DD
0.6V
2.6V
V
OH
I
OH
+
-
HI1175 HI1175
A/D D/ADSP/µP
REFERENCE
ICL8069
AMP
AMP
HI1175
12
Static Performance Definitions
Offset, full scale, and gain all use a measured value of the
internal voltage reference to determine the ideal plus and
minus full scale values. The results are all displayed in
LSBs.
Offset Error (E
OB
)
The first code transition should occur at a level
1
/
2
LSB
above the bottom reference voltage. Offset is defined as the
deviation of the actual code transition from this point. Note
that this is adjustable to zero.
Full Scale Error (E
OT
)
The last code transition should occur for a analog input that
is 1
1
/
2
LSBs below full scale. Full scale error is defined as
the deviation of the actual code transition from this point.
Differential Linearity Error (DNL)
DNL is the worst case deviation of a code width from the
ideal value of 1 LSB. The converter is guaranteed to have no
missing codes.
Integral Linearity Error (INL)
INL is the worst case deviation of a code center from a best
fit straight line calculated from the measured data.
Dynamic Performance Definitions
Fast Fourier Transform (FFT) techniques are used to
evaluate the dynamic performance of the HI1175. A low
distortion sine wave is applied to the input, it is sampled, and
the output is stored in RAM. The data is then transformed
into the frequency domain with a 1024 point FFT and
analyzed to evaluate the dynamic performance of the A/D.
The sine wave input to the part is -0.5dB down from fullscale
for all these tests. The distortion numbers are quoted in dBc
(decibels with respect to carrier) and DO NOT include any
correction factors for normalizing to fullscale.
Signal-to-Noise Ratio (SNR)
SNR is the measured RMS signal to RMS noise at a
specified input and sampling frequency. The noise is the
RMS sum of all of the spectral components except the
fundamental and the first five harmonics.
Signal-to-Noise + Distortion Ratio (SINAD)
SINAD is the measured RMS signal to RMS sum of all
other spectral components below the Nyquist frequency
excluding DC.
Effective Number Of Bits (ENOB)
The effective number of bits (ENOB) is derived from the
SINAD data. ENOB is calculated from:
ENOB = (SINAD - 1.76 + V
CORR
) / 6.02,
where: V
CORR
= 0.5dB.
Total Harmonic Distortion
This is the ratio of the RMS sum of the first 5 harmonic
components to the RMS value of the measured input signal.
2nd and 3rd Harmonic Distortion
This is the ratio of the RMS value of the 2nd and 3rd
harmonic component respectively to the RMS value of the
measured input signal.
Spurious Free Dynamic Range (SFDR)
SFDR is the ratio of the fundamental RMS amplitude to the
RMS amplitude of the next largest spur or spectral
component. If the harmonics are buried in the noise floor it is
the largest peak.
Full Power Input Bandwidth
Full power bandwidth is the frequency at which the
amplitude of the digitally reconstructed output has
decreased 3dB below the amplitude of the input sine wave.
The input sine wave has a peak-to-peak amplitude equal to
the reference voltage. The bandwidth given is measured at
the specified sampling frequency.
Timing Definitions
Sampling Delay (t
SD
)
Sampling delay is the time delay between the external
sample command (the falling edge of the clock) and the time
at which the signal is actually sampled. This delay is due to
internal clock path propagation delays.
Aperture Jitter (t
AJ
)
This is the RMS variation in the sampling delay due to
variation of internal clock path delays.
Data Latency (t
LAT
)
After the analog sample is taken, the data on the bus is
available after 2.5 cycles of the clock. This is due to the
architecture of the converter where the data has to ripple
through the stages. This delay is specified as the data
latency. After the data latency time, the data representing
each succeeding sample is output at the following clock
pulse. The digital data lags the analog input by 2.5 cycles.
Output Data Delay (t
D
)
Output Data Delay is the delay time from when the data is
valid (rising clock edge) to when it shows up at the output
bus. This is due to internal delays at the digital output.
HI1175

HI1175JCB-T

Mfr. #:
Manufacturer:
Renesas / Intersil
Description:
IC ADC 8BIT FLASH 24SOIC
Lifecycle:
New from this manufacturer.
Delivery:
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