NCP1082
http://onsemi.com
14
DC−DC Converter Controller
The NCP1082 implements a current mode DC−DC converter controller which is illustrated in Figure 14.
VDDL
FB
CS
360 mV
Oscillator
COMP
SS
Gate
Driver
PWM comp
OSC
VDDL
VDDL
Blanking
time
Current Slope
Compensation
2
Soft−start
R
S
Q
1.45 V
1.2 V
Current limit
comp
0
9 V LDO
3.3 V LDO
GATE
VDDH
ARTN
VPORTP
Set
CLK
Reset
CLK
Figure 14. DC−DC Controller Block Diagram
5 kW
10 mA
11 kW
5 mA
&
Sawtooth
Generator
Internal VDDH and VDDL Regulators and Gate Driver
An internal linear regulator steps down the VPORTP
voltage to a 9 V output on the VDDH pin. VDDH supplies
the internal gate driver circuit which drives the GATE pin
and the gate of the external power MOSFET. The NCP1082
gate driver supports an external MOSFET with high Vth and
high input gate capacitance. A second LDO regulator steps
down the VDDH voltage to a 3.3 V output on VDDL. VDDL
powers the analog circuitry of the DC−DC controller.
In order to prevent uncontrolled operations, both regulators
include power−on−reset (POR) detectors which prevent the
DC−DC controller from operating when either VDDH or
VDDL is too low. In addition, an over−voltage lockout
(OVLO) on the VDDH supply disables the gate driver in case
of an open−loop converter with a configuration using the bias
winding of the transformer (see Figure 4).
Both VDDH and VDDL regulators turn on as soon as
VPORT reaches the Vuvlo_on threshold.
Error Amplifier
In non−isolated converter topologies, the high gain
internal error amplifier of the NCP1082 and the internal
1.2 V reference voltage regulate the DC−DC output voltage.
In this configuration, the feedback loop compensation
network should be inserted between the FB and COMP pins
as shown in Figures 3, 4 and 5.
In isolated topologies the error amplifier is not used
because it is already implemented externally with the shunt
regulator on the secondary side of the DC−DC controller
(see Figure 2). Therefore the FB pin must be strapped to
ARTN and the output transistor of the opto−coupler has to
be connected on the COMP pin where an internal 5 kW
pull−up resistor is tied to the VDDL supply (see Figure 14).
Soft−Start
The soft−start function provided by the NCP1082 allows
the output voltage to ramp up in a controlled fashion,
eliminating output voltage overshoot. This function is
programmed by connecting a capacitor C
SS
between the SS
and ARTN pins.
While the DC−DC controller is in POR, the capacitor C
SS
is fully discharged. After coming out of POR, an internal
current source of 5 mA typically starts charging the capacitor
C
SS
to initiate soft−start. When the voltage on SS pin has
reached 0.45 V (typical), the gate driver is enabled and
DC−DC operation starts with a duty cycle limit which
increases with the SS pin voltage. The soft−start function is
finished when the SS pin voltage goes above 1.6 V for which
the duty cycle limit reaches its maximum value of 80
percent.
Soft−start can be programmed by using the following
equation:
t
SS
(ms) + 0.23 C
SS
(nF)
