HMC1114 Data Sheet
Rev. A | Page 12 of 15
THEORY OF OPERATION
The HMC1114 is a 10 W, gallium nitride (GaN), power amplifier
that consists of two gain stages in series, and the basic block
diagram for the amplifier is shown in Figure 40.
V
DD1
V
GG1
RFIN RFOUT
V
GG2
V
DD2
V
DD2
13530-140
Figure 40. Basic Block Diagram
The recommended dc bias conditions put the device in deep
Class AB operation, resulting in high P
SAT
(41.5 dBm typical) at
improved levels of PAE (54% typical). The voltage applied to the
V
GG1
and V
GG2
pads sets the gate bias of the field effect transistors
(FETs), providing control of the drain current. For this reason,
the application of a bias voltage to the V
GG1
and V
GG2
pads is
required and not optional.
The HMC1114 has single-ended input and output ports whose
impedances are nominally equal to 50 Ω over the 2.7 GHz to
3.8 GHz frequency range. Consequently, it can directly insert
into a 50 Ω system with no required impedance matching
circuitry, which also means that multiple HMC1114 amplifiers
can be cascaded back to back without the need for external
matching circuitry. The input and output impedances are
sufficiently stable vs. variations in temperature and supply
voltage that no impedance matching compensation is required.
Note that it is critical to supply very low inductance ground
connections to the GND pins and the package base exposed pad
to ensure stable operation. To achieve optimal performance
from the HMC1114 and prevent damage to the device, do not
exceed the absolute maximum ratings.
Data Sheet HMC1114
Rev. A | Page 13 of 15
APPLICATIONS INFORMATION
Figure 41 shows the basic connections for operating the HMC1114.
The RFIN port is dc-coupled. An appropriate valued external dc
block capacitor is required at RFIN port. The RFOUT port has
on-chip dc block capacitors that eliminate the need for external ac
coupling capacitors.
RECOMMENDED BIAS SEQUENCE
During Power-Up
The recommended bias sequence during power-up is the
following:
1. Connect to ground.
2. Set V
GG1
and V
GG2
to 8 V.
3. Set V
DD1
and V
DD2
to 28 V.
4. Increase V
GG1
and V
GG2
to achieve a typical I
DQ
= 150 mA.
5. Apply the RF signal.
During Power-Down
The recommended bias sequence during power-down is the
following:
1. Turn off the RF signal.
2. Decrease V
GG1
to −8 V to achieve a typical I
DQ
= 0 mA.
3. Decrease V
DD1
and V
DD2
t o 0 V.
4. Increase V
GG1
to 0 V.
Unless otherwise noted, all measurements and data shown were
taken using the typical application circuit (see Figure 41) on the
evaluation board (see Figure 42) and biased per the conditions
in the Recommended Bias Sequence section. The V
DD1
and two
V
DD2
pins are connected together. Similarly, the V
GG1
and V
GG2
pins are also connected together. The bias conditions shown in
the Recommended Bias Sequence section are the operating
points recommended to optimize the overall performance.
Operation using other bias conditions may provide performance
that differs from what is in Table 1 and Table 2. Increasing the
V
DD1
and V
DD2
levels typically increase gain and P
SAT
at the
expense of power consumption. This behavior is seen in the
Typical Performance Characteristics section. For applications
where the P
SAT
requirement is not stringent, reduce the V
DD1
and
the V
DD2
of the HMC1114 to improve power consumption. To
obtain the best performance while not damaging the device,
follow the recommended biasing sequence outlined in the
Recommended Bias Sequence section.
TYPICAL APPLICATION CIRCUIT
17
1
3
4
2
9
5
6
7
8
18
19
20
21
22
23
24
12
11
10
13
14
15
16
25
26
27
28
29
30
31
32
C2
1000pF
V
DD1
, V
DD2
V
GG1
, V
GG2
RFIN RFOUT
C3
1µF
C8
10µF
C6
10µF
C4
1µF
C9
10µF
C5
1µF
C10
10µF
C7
10µF
C1
1000pF
13530-040
HMC1114
Figure 41. Typical Application Circuit
HMC1114 Data Sheet
Rev. A | Page 14 of 15
EVALUATION PRINTED CIRCUIT BOARD (PCB)
The EV1HMC1114LP5D (600-01209-00) evaluation PCB is
shown in Figure 42.
BILL OF MATERIALS
Use RF circuit design techniques for the circuit board used in
the application. Provide 50 impedance for the signal lines and
directly connect the package ground leads and exposed paddle
to the ground plane, similar to that shown in Figure 42. Use a
sufficient number of via holes to connect the top and bottom
ground planes. The evaluation PCB shown in Figure 42 is
available from Analog Devices, Inc., upon request.
J3
1
GND
GND
VDD1/VDD2
C7C8
C6
C1
C3
C2
U1
C4
C9
C5
C10
JP1
RFIN
J1 J2
RFOUT
VGG1/VGG2
13530-041
Figure
42. Evaluation Printed Circuit Board (PCB)
Table 6. Bill of Materials for Evaluation PCB EV1HMC1114LP5D (600-01209-00)
Item Description
J1, J2 SMA connectors
J3 DC pins
JP1
Preform jumper
C1, C2 1000 pF capacitors, 0603 package
C3 to C6 1 µF capacitors, 0603 package
C7 to C10 10 µF capacitors, 1210 package
U1 HMC1114LP5DE
PCB 600-01209-00 evaluation PCB; circuit board material: Rogers 4350 or Arlon 25FR

EV1HMC1114LP5D

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
RF Development Tools EVALUATION PCB ASSEMBLY
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

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