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EV1HMC1114LP5D

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P16
Data Sheet HMC1114
Rev. A | Page 3 of 15
SPECIFICATIONS
ELECTRICAL SPECIFICATIONS
T
A
= 25°C, V
DD
= 28 V, I
DQ
= 150 mA, frequency range = 2.7 GHz to 3.2 GHz, unless otherwise noted.
Table 1.
Parameter Symbol Min Typ Max Unit Test Conditions/Comments
FREQUENCY RANGE 2.7 3.2 GHz
GAIN
Small Signal Gain 32 35 dB
Gain Flatness ±0.5 dB
Power Gain for 4 dB Compression 29 dB
Power Gain for Saturated Output Power 25.5 dB Measurement taken at P
IN
= 16 dBm
RETURN LOSS
Input 14 dB
Output
11
dB
POWER
Output Power for 4 dB Compression
39
dBm
Saturated Output Power P
SAT
41.5 dBm Measurement taken at P
IN
= 16 dBm
Power Added Efficiency PAE 54 %
OUTPUT THIRD-ORDER INTERCEPT IP3 44 Measurement taken at P
OUT
/tone = 30 dBm
TARGET QUIESCENT CURRENT I
DQ
150 mA Adjust the gate control voltage (V
GG1
, V
GG2
) between
−8 V and 0 V to achieve an I
DQ
= 150 mA typical
T
A
= 25°C, V
DD
= 28 V, I
DQ
= 150 mA, frequency range = 3.2 GHz to 3.8 GHz, unless otherwise noted.
Table 2.
Parameter Symbol Min Typ Max Unit Test Conditions/Comments
FREQUENCY RANGE 3.2 3.8 GHz
GAIN
Small Signal Gain
29
32
dB
Gain Flatness ±1 dB
Power Gain for 4 dB Compression 28 dB
Power Gain for Saturated Output Power 25 dB Measurement taken at P
IN
= 16 dBm
RETURN LOSS
Input 25 dB
Output 9 dB
POWER
Output Power for 4 dB Compression P4dB 40 dBm
Saturated Output Power P
SAT
40.5 dBm Measurement taken at P
IN
= 16 dBm
Power Added Efficiency PAE 53 %
OUTPUT THIRD-ORDER INTERCEPT IP3 44 Measurement taken at P
OUT
/tone = 30 dBm
TARGET QUIESCENT CURRENT I
DQ
150 mA Adjust the gate control voltage (V
GG1
, V
GG2
) between
−8 V and 0 V to achieve an I
DQ
= 150 mA typical
TOTAL SUPPLY CURRENT BY V
DD
Table 3.
Parameter Symbol Min Typ Max Unit Test Conditions/Comments
SUPPLY CURRENT I
DQ
Adjust V
GG1
, V
GG2
to achieve an I
DQ
= 150 mA typical
V
DD
= 25 V 150 mA
V
DD
= 28 V 150 mA
V
DD
= 32 V 150 mA
HMC1114 Data Sheet
Rev. A | Page 4 of 15
ABSOLUTE MAXIMUM RATINGS
Table 4.
Parameter Rating
Drain Bias Voltage (V
DD1
, V
DD2
) 35 V dc
Gate Bias Voltage (V
GG1
, V
GG2
)
−8 V to 0 V dc
RF Input Power (RFIN) 30 dBm
Maximum Forward Gate Current 4 mA
Continuous Power Dissipation, P
DISS
(T
A
= 85°C,
Derate 227 mW/°C Above 120°C)
24 W
Thermal Resistance, Junction to Back of Paddle 4.4°C/W
Channel Temperature
225°C
Maximum Peak Reflow Temperature (MSL3)
1
260°C
Storage Temperature Range −40°C to +125°C
Operating Temperature Range −40°C to +85°C
ESD Sensitivity (Human Body Model) Class 1A,
passed 250 V
1
See the Ordering Guide section.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
ESD CAUTION
Data Sheet HMC1114
Rev. A | Page 5 of 15
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
17
1
3
4
2
9
GND
GND
GND
RFIN
5
6
RFIN
GND
7
GND
8
GND
GND
18
GND
19
GND
20
RFOUT
21
RFOUT
22
GND
23
GND
24
GND
GND
12
GND
11
GND
10
V
GG1
13
V
GG2
14
GND
15
GND
16
GND
25
GND
26
V
DD2
27
V
DD2
28
GND
29
GND
30
V
DD1
31
GND
32
GND
HMC1114
TOP VIEW
(Not to Scale)
13530-002
NOTES
1. EXPOSED PAD. EXPOSED PAD MUST
BE CONNECTED TO RF/DC GROUND.
Figure 2. Pin Configuration
Table 5. Pin Function Descriptions
Pin No. Mnemonic Description
1 to 3, 6 to 9, 11, 12, 14 to
19, 22 to 25, 28, 29, 31, 32
GND
Ground. These pins and the package bottom (EPAD) must be connected to RF/dc ground. See
Figure 3 for the GND interface schematic.
4, 5 RFIN RF Input. These pins are dc-coupled and matched to 50 Ω. See Figure 4 for the RFIN interface
schematic.
10, 13 V
GG1
, V
GG2
Gate Control Voltage Pins. External bypass capacitors of 1 μF and 10 μF are required. See
Figure 5 for the V
GG1
and V
GG2
interface schematic.
20, 21 RFOUT RF Output. These pins are ac-coupled and matched to 50 Ω. See Figure 6 for the RFOUT
interface schematic.
26, 27, 30 V
DD1
, V
DD2
Drain Bias Pins for the Amplifier. External bypass capacitors of 100 pF, 1 μF, and 10 μF are
required. See Figure 7 for the V
DD1
and V
DD2
interface schematic.
EPAD Exposed Pad. The exposed pad must be connected to RF/dc ground.
INTERFACE SCHEMATICS
GND
13530-003
Figure 3. GND Interface
RFIN
13530-004
Figure 4. RFIN Interface
V
GG1
, V
GG2
13530-005
Figure 5. V
GG1
and V
GG2
Interface
RFOUT
13530-006
Figure 6. RFOUT Interface
V
DD1
, V
DD2
13530-007
Figure 7. V
DD1
and V
DD2
Interface
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P16

EV1HMC1114LP5D

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Manufacturer:
Analog Devices Inc.
Description:
RF Development Tools EVALUATION PCB ASSEMBLY
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