9DB1904BKLFT Datasheet 9DB1904BKLF, 9DB1904BKLFT | P13-P15

IDT

19 Output Differential Buffer for PCIe Gen2 and QPI 1607C—04/19/11

9DB1904B

19 Output Differential Buffer for PCIe Gen2 and QPI

General SMBus serial interface information for the 9DB1904B

How to Write:

• Controller (host) sends a start bit.

• Controller (host) sends the write address D4

(h)

• IDT clock will

acknowledge

• Controller (host) sends the begining byte location = N

• IDT clock will

acknowledge

• Controller (host) sends the data byte count = X

• IDT clock will

acknowledge

• Controller (host) starts sending

Byte N through

Byte N + X -1

• IDT clock will

acknowledge

each byte

one at a time

• Controller (host) sends a Stop bit

How to Read:

• Controller (host) will send start bit.

• Controller (host) sends the write address D4

(h)

• IDT clock will

acknowledge

• Controller (host) sends the begining byte

location = N

• IDT clock will

acknowledge

• Controller (host) will send a separate start bit.

• Controller (host) sends the read address D5

(h)

• IDT clock will

acknowledge

• IDT clock will send the data byte count = X

• IDT clock sends

Byte N + X -1

• IDT clock sends

Byte 0 through byte X (if X

(h)

was written to byte 8)

• Controller (host) will need to acknowledge each byte

• Controllor (host) will send a not acknowledge bit

• Controller (host) will send a stop bit

T starT bit

WR WRite

RT Repeat starT

RD ReaD

Beginning Byte N

Byte N + X - 1

N Not acknowledge

PstoP bit

IDT (Slave/Receiver)

Controller (Host)

X Byte

ACK

Data Byte Count = X

ACK

Slave Address D5

(h)

Index Block Read Operation

Slave Address D4

(h)

Beginning Byte = N

ACK

IDT (Slave/Receiver)

ACK

PstoP bit

X Byte

Index Block Write Operation

Slave Address D4

(h)

Beginning Byte = N

WRite

starT bit

Controller (Host)

Byte N + X - 1

Data Byte Count = X

Beginning Byte N

IDT

19 Output Differential Buffer for PCIe Gen2 and QPI 1607C—04/19/11

9DB1904B

19 Output Differential Buffer for PCIe Gen2 and QPI

SMBusTable: Reserved Register

Pin # Name Control Function T

e0 1PWD

Bit 7 R

Bit 6 R

Bit 5 R

Bit 4 R

Bit 3 R

Bit 2 R

Bit 1 R

Bit 0 R

SMBusTable: Output Control Register

Pin # Name Control Function T

e0 1PWD

Bit 7

DIF_7 Output Control RW Hi-Z Enable 1

Bit 6

DIF_6 Output Control RW Hi-Z Enable 1

Bit 5

DIF_5 Output Control RW Hi-Z Enable 1

Bit 4

DIF_4 Output Control RW Hi-Z Enable 1

Bit 3

DIF_3 Output Control RW Hi-Z Enable 1

Bit 2

DIF_2 Output Control RW Hi-Z Enable 1

Bit 1

DIF_1 Output Control RW Hi-Z Enable 1

Bit 0

DIF_0 Output Control RW Hi-Z Enable 1

SMBusTable: Output and PLL BW Control Register

Pin # Name Control Function T

e0 1PWD

Bit 7

RW Hi

h B

Low B

Bit 6

RW B

pass PLL

Bit 5

DIF_13 Output Control RW Hi-Z Enable 1

Bit 4

DIF_12 Output Control RW Hi-Z Enable 1

Bit 3

DIF_11 Output Control RW Hi-Z Enable 1

Bit 2

DIF_10 Output Control RW Hi-Z Enable 1

Bit 1

DIF_9 Output Control RW Hi-Z Enable 1

Bit 0

DIF_8 Output Control RW Hi-Z Enable 1

Note: Bit 7 is wired OR to the HIGH_BW# input, any 0 selects High BW

Note: Bit 6 is wired OR to the SMB_A2_PLLBYP# input, any 0 selects Fanout Bypass mode

SMBusTable: Output Enable Readback Register

Pin # Name Control Function T

e0 1PWD

Bit 7

R X

Bit 6

R X

Bit 5

R X

Bit 4

R X

Bit 3

R X

Bit 2

R X

Bit 1

R X

Bit 0

R X72

see note PLL_BW# ad

ust

see note BYPASS# test mode / PLL

te 3

te 1

te 0

Reserved

Readback - OE9# Input

Readback - OE8# Input

Readback

Readback - OE7# Input

ReadbackReadback - OE_01234# Input

Readback

Readback - OE5# Input

Readback - OE6# Input

Readback

Readback - SMB_A2_PLLBYP# In Readback

Readback - HIGH_BW# In Readback

te 2

Reserved

IDT

19 Output Differential Buffer for PCIe Gen2 and QPI 1607C—04/19/11

9DB1904B

19 Output Differential Buffer for PCIe Gen2 and QPI

SMBusTable: Output Enable Readback Register

Pin # Name Control Function T

e0 1PWD

Bit 7

R X

Bit 6

R X

Bit 5

Bit 4

R X

Bit 3

R X

Bit 2

R X

Bit 1

R X

Bit 0

R X

SMBusTable: Vendor & Revision ID Register

Pin # Name Control Function T

e0 1PWD

Bit 7

RID3 R - - 0

Bit 6

RID2 R - - 0

Bit 5

RID1 R - - 0

Bit 4

RID0 R - - 1

Bit 3

VID3 R - - 0

Bit 2

VID2 R - - 0

Bit 1

VID1 R - - 0

Bit 0

VID0 R - - 1

SMBusTable: DEVICE ID (194 Decimal or C2 Hex)

Pin # Name Control Function T

e0 1PWD

Bit 7

RW 1

Bit 6

RW 1

Bit 5

RW 0

Bit 4

RW 0

Bit 3

RW 0

Bit 2

RW 0

Bit 1

RW 1

Bit 0

RW 0

SMBusTable: Byte Count Register

Pin # Name Control Function T

e0 1PWD

Bit 7

BC7 RW - - 0

Bit 6

BC6 RW - - 0

Bit 5

BC5 RW - - 0

Bit 4

BC4 RW - - 0

Bit 3

BC3 RW - - 0

Bit 2

BC2 RW - - 1

Bit 1

BC1 RW - - 1

Bit 0

BC0 RW - - 1

Reserved

Readback

Reserved

Readback

Reserved

Device ID 1 Reserved

Writing to this register

configures how many

bytes will be read back.

Device ID 3

Device ID 4

Readback - OE12# Input

VENDOR ID

Readback - OE11# Input

Device ID 5

Device ID 6

Device ID 7 (MSB)

te 5

te 6

Reserved

Device ID 2

te 4

te 7

Reserved

REVISION ID

Readback

Readback - OE10# Input

Readback - OE14# Input

Readback

Readback - OE13# Input

Readback - OE15_16# Input

Readback - OE17_18# Input Readback

ReservedDevice ID 0

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18

9DB1904BKLFT

Mfr. #:

Buy 9DB1904BKLFT

Manufacturer:

IDT

Description:

Clock Buffer 19 OUTPUT PCIE GEN2 BUFFER w/QPI

Lifecycle:

New from this manufacturer.

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9DB1904BKLFT

9DB1904BKLFT

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