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9DB1904BKLFT

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18
IDT
®
19 Output Differential Buffer for PCIe Gen2 and QPI 1607C—04/19/11
9DB1904B
19 Output Differential Buffer for PCIe Gen2 and QPI
4
Functional Block Diagram
Power Groups
CLK_IN
CLK_IN#
DIF(18:0)
HIGH_BW#
SMB_A2_PLLBYP#
SMBDAT
SMBCLK
CKPWRGD_PD#
19
IREF
OE(17_18)#
OE(15_16)#
OE(14:5)#,
OE_01234#
13
SMB_A0
SMB_A1
100M_133M#_LV
PLL
(SS Compatible)
Logic
VDD GND
3 2 PLL, Analog
11,27,47,63 10,28,46,64 DIF clocks
Description
Pin Number
Byte 9,
bit 2
100M_133M#_LV
Byte9,
bit 1
FSB
Byte 9,
bit 0
FSA
CLK_IN
MHz
DIF Outputs
MHz
Notes
1 0 1 100.00 100.00
1
0 0 1 133.33 133.33
2
Notes:FS_A_410 = 1
1. Powerup Default for 100M_133M# = 1
2. Powerup Default for 100M_133M# = 0
9DB1904 Frequency Selects for PLL Mode
IDT
®
19 Output Differential Buffer for PCIe Gen2 and QPI 1607C—04/19/11
9DB1904B
19 Output Differential Buffer for PCIe Gen2 and QPI
5
Electrical Characteristics - Absolute Maximum Ratings
PARAMETER SYMBOL CONDITIONS
MIN TYP MAX
UNITS NOTES
3.3V Core Supply Voltage VDDA 4.6 V 1,2
3.3V Logic Supply Voltage VDD 4.6 V 1,2
Input Low Voltage V
IL
GND-0.5 V 1
Input High Voltage V
IH
Except for SMBus interface V
DD
+0.5V V 1
Input High Voltage V
IHSMB
SMBus clock and data pins 5.5V V 1
Storage Temperature Ts -65 150
°
C
1
Junction Temperature Tj 125 °C 1
Input ESD protection
ESD prot Human Body Model 2000 V 1
1
Guaranteed b
y
desi
g
n and characterization, not 100% tested in production.
2
Operation under these conditions is neither implied nor
g
uaranteed.
Electrical Characteristics - Clock Input Parameters
TA = T
COM;
Supply Voltage VDD/VDDA = 3.3 V +/-5%, See Test Loads for Loading Conditions
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES
Input High Voltage - DIF_IN V
I HDI F
Differential inputs
(single-ended measurement)
600 800 1150 mV 1
Input Low Voltage - DIF_IN V
ILDIF
Differential inputs
(single-ended measurement)
V
SS
- 300 0 300 mV 1
Input Common Mode
Voltage - DIF_IN
V
COM
Common Mode Input Voltage 300 1000 mV 1
Input Amplitude - DIF_IN V
SWING
Peak to Peak value 300 1450 mV 1
Input Slew Rate - DIF_IN dv/dt Measured differentially 0.4 8 V/ns 1,2
Input Leakage Current I
IN
V
IN
= V
DD ,
V
IN
=
GND -5 5 uA 1
Input Duty Cycle d
tin
Measurement from differential wavefrom 45 55 % 1, 3
Input Jitter - Cycle to Cycle J
DI FI n
Differential Measurement 0 125 ps 1
1
Guaranteed b
y
desi
g
n and characterization, not 100% tested in production.
2
Slew rate measured throu
g
h +/-75mV window centered around differential zero
3
Input dut
y
c
y
cle will directl
y
impact output dut
y
c
y
cle in b
y
pass mode. It has no impact in PLL mode.
Electrical Characteristics - Current Consumption
TA = T
COM;
Supply Voltage VDD/VDDA = 3.3 V +/-5%, See Test Loads for Loading Conditions
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES
I
DD3.3OP
VDD, All outputs active @100MHz
425 450
mA 1
I
DD3.3AOP
VDDA, All outputs active @100MHz
35 45
mA 1
I
DD3. 3PD
VDD 20 25 mA 1
I
DD3.3APD
VDDA 12 15 mA 1
1
Guaranteed by design and characterization, not 100% tested in production. Zo = 100
Ω
Powerdown Current
Operating Supply Current
IDT
®
19 Output Differential Buffer for PCIe Gen2 and QPI 1607C—04/19/11
9DB1904B
19 Output Differential Buffer for PCIe Gen2 and QPI
6
Electrical Characteristics - Input/Supply/Common Parameters
TA = T
COM;
Supply Voltage VDD/VDDA = 3.3 V +/-5%, See Test Loads for Loading Conditions
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES
Ambient Operating
Temperature
T
COM
Commmercial range 0 70 °C 1
Input High Voltage V
IH
Single-ended inputs, except SMBus, low
threshold and tri-level inputs
2V
DD
+ 0.3 V 1
Input Low Voltage V
IL
Single-ended inputs, except SMBus, low
threshold and tri-level inputs
GND
- 0.3 0.8 V 1
Low Threshold Input-
High Voltage
V
IH_FS
3.3 V +/-5%, Applies to 100M_133M#_LV pin 0.7 V
DD
+ 0.3 V 1
Low Threshold Input-
Low Voltage
V
IL_FS
3.3 V +/-5%, Applies to 100M_133M#_LV pin V
SS
- 0.3 0.35 V 1
I
IN
Single-ended inputs, V
IN
= GND, V
IN
= VDD -5 5 uA 1
I
INP
Single-ended inputs
V
IN
= 0 V; Inputs with internal pull-up resistors
V
IN
= VDD; Inputs with internal pull-down resistors
-200 200 uA 1
F
ib
yp
V
DD
= 3.3 V, Bypass mode 33 400 MHz 2
F
i
p
ll
V
DD
= 3.3 V, 100MHz PLL mode 90 100.00 110 MHz 2
F
i
p
ll
V
DD
= 3.3 V, 133.33MHz PLL mode 120 133.33 147 MHz 2
Pin Inductance L
in
7nH1
C
IN
Logic Inputs, except DIF_IN 1.5 5 pF 1
C
I NDI F_I N
DIF_IN differential clock inputs 1.5 2.7 pF 1,4
C
OUT
Output pin capacitance 6 pF 1
Clk Stabilization T
STAB
From V
DD
Power-Up and after input clock
stabilization or de-assertion of PD# to 1st clock
1.8 ms 1,2
Input SS Modulation
Frequency
f
MODIN
Allowable Frequency
(Triangular Modulation)
30 33 kHz 1
OE# Latency t
LATOE#
DIF start after OE# assertion
DIF stop after OE# deassertion
412clocks1,3
Tdrive_PD# t
DRVPD
DIF output enable after
PD# de-assertion
300 us 1,3
Tfall t
F
Fall time of control inputs 5 ns 1,2
Trise t
R
Rise time of control inputs 5 ns 1,2
SMBus Input Low Voltage V
ILSMB
0.8 V 1
SMBus Input High Voltage V
IHSMB
2.1 V
DDSMB
V1
SMBus Output Low Voltage V
OLSMB
@ I
PULLUP
0.4 V 1
SMBus Sink Current I
PULLUP
@ V
OL
4mA1
Nominal Bus Voltage V
DDSMB
3V to 5V +/- 10% 2.7 5.5 V 1
SCLK/SDATA Rise Time t
RSMB
(Max VIL - 0.15) to (Min VIH + 0.15) 1000 ns 1
SCLK/SDATA Fall Time t
FSMB
(Min VIH + 0.15) to (Max VIL - 0.15) 300 ns 1
SMBus Operating
Frequency
f
MAXSMB
Maximum SMBus operating frequency 100 kHz 1,5
1
Guaranteed by design and characterization, not 100% tested in production.
2
Control input must be monotonic from 20% to 80% of input swing.
5
The differential in
p
ut clock must be runnin
g
for the SMBus to be active
Input Current
3
Time from deassertion until out
p
uts are >200 mV
4
DIF_IN input
Capacitance
Input Frequency
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18

9DB1904BKLFT

Mfr. #:
Buy 9DB1904BKLFT
Manufacturer:
IDT
Description:
Clock Buffer 19 OUTPUT PCIE GEN2 BUFFER w/QPI
Lifecycle:
New from this manufacturer.
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