IDT
®
19 Output Differential Buffer for PCIe Gen2 and QPI 1607C—04/19/11
9DB1904B
19 Output Differential Buffer for PCIe Gen2 and QPI
8
Electrical Characteristics - Output Duty Cycle, Jitter, Skew and PLL Characterisitics
TA = T
COM;
Supply Voltage VDD = 3.3 V +/-5%
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES
-3dB point in High BW Mode 2 3 4 MHz 1
-3dB point in Low BW Mode 0.7 1 1.4 MHz 1
PLL Jitter Peaking t
JPEAK
Peak Pass band Gain 1.4 2 dB 1
Duty Cycle t
DC
Measured differentially, PLL Mode 45 49.5 55 % 1,2
Duty Cycle Distortion t
DCD
Measured differentially, Bypass Mode
@100MHz
-2 1 2 % 1,2,5
t
pdBYP
Bypass Mode, nominal value @ 25°C, 3.3V,
V
T
= 50%
2500 3700 4500 ps 1,2,4
t
pdPLL
PLL Mode, nominal value @ 25°C, 3.3V,
V
T
= 50%
100 300 500 ps 1,2,3
DIF_IN, DIF [x:0]
Δ
t
pd_BYP
Input-to-Output Skew Variation in Bypass
mode
(over specified voltage / temperature operating
ranges)
|500| |600| ps
1,2,4,6,7,
8,9,13
DIF_IN, DIF [x:0]
Δ
t
pd_PLL
Input-to-Output Skew Variation in PLL mode
(over specified voltage / temperature operating
ranges)
|250| |350| ps
1,2,3,6,7,
8,9,13
DIF[X:0] t
JPH
Differential Phase Jitter (RMS Value) 2 10 ps 1,7,10
DIF[X:0] t
SSTERROR
Differential Spread Spectrum Tracking Error
eak to
eak
40 80 ps 1,7,12
Skew, Output to Output t
sk3
V
T
= 50% 100 150 ps 1
PLL mode 40 50 ps 1,2
Additive Jitter in Bypass Mode 25 50 ps 1,2
1
Guaranteed by design and characterization, not 100% tested in production. C
LOA
= 2pF
5
Duty cycle distortion is the difference in duty cycle between the output and the input clock when the device is operated in bypass mode.
6
VT = 50% of Vout
11
t is the period of the input clock
Jitter, Cycle to cycle
7
This parameter is deterministic for a given device
8
Measured with scope averaging on to find mean value.
9
Long-term variation from nominal of input-to-output skew over temperature and voltage for a single device.
10
This parameter is measured at the outputs of two separate 9DB1904 devices driven by a single main clock. The 9DB1904's must
be set to high bandwidth. Differential phase jitter is the accumulation of the phase jitter not shared by the outputs (eg. not including
the affects of spread spectrum). Target ranges of consideration are agents with BW of 1-22MHz and 11-33MHz.
12
Differential spread spectrum tracking error is the difference in spread spectrum tracking between two 9DB1904 devices This
parameter is measured at the outputs of two separate 9DB1904 devices driven by a single main clock in Spread Spectrum mode.
The 9DB1904's must be set to high bandwidth. The spread spectrum characteristics are: maximum of 0.5%, 30-33KHz modulation
frequency, linear profile.
PLL Bandwidth BW
Skew, Input to Output
13
This parameter is an absolute value. It is not a double-sided figure.
t
jcyc-cyc
2
Measured from differential cross-point to differential cross-point
3
PLL mode Input-to-Output skew is measured at the first output edge following the corresponding input.
4
All Bypass Mode Input-to-Output specs refer to the timing between an input edge and the specific output edge created by it.
