Philips Semiconductors Product data
74AVC16835A
18-bit registered driver with
Dynamic Controlled Outputs (3-State)
2
2002 Mar 15 853-2208 27859
FEATURES
• Wide supply voltage range of 1.2 V to 3.6 V
• Complies with JEDEC standard no. 8-1A/5/7
• CMOS low power consumption
• Input/output tolerant up to 3.6 V
• DCO (Dynamic Controlled Output) circuit dynamically changes
output impedance, resulting in noise reduction without speed
degradation
• Low inductance multiple V
CC
and GND pins for minimum noise
and ground bounce
• Power off disables 74AVC16835A outputs, permitting Live
Insertion
• Integrated input diodes to minimize input overshoot and
undershoot
• Full PC133 solution provided when used with PCK2509S or
PCK2510S and CBT16292
DESCRIPTION
The 74AVC16835A is a 18-bit universal bus driver. Data flow is
controlled by output enable (OE
), latch enable (LE) and clock inputs
(CP).
This product is designed to have an extremely fast propagation
delay and a minimum amount of power consumption.
To ensure the high-impedance state during power up or power
down, OE
should be tied to V
CC
through a pullup resistor (Live
Insertion).
A Dynamic Controlled Output (DCO) circuitry is implemented to
support termination line drive during transient. See the graphs on
page 8 for typical curves.
PIN CONFIGURATION
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28 29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56NC
NC
Y
0
Y
1
Y
2
Y
3
Y
4
Y
5
GND
V
CC
GND
Y
6
Y
7
Y
8
Y
9
Y
10
Y
11
GND
Y
12
Y
13
Y
14
V
CC
Y
15
Y
16
GND
Y
17
OE
LE
GND
NC
A
0
GND
A
1
A
2
V
CC
A
3
A
4
A
5
GND
A
6
A
7
A
8
A
9
A
10
A
11
GND
A
12
A
13
A
14
V
CC
A
15
A
16
GND
A
17
CP
GND
SH00130
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25°C; t
r
= t
f
≤ 2.0 ns; C
L
= 30 pF.
SYMBOL
PARAMETER CONDITIONS TYPICAL UNIT
t
PHL
/t
PLH
Propagation delay
An to Yn
V
CC
= 1.8 V
V
CC
= 2.5 V
V
CC
= 3.3 V
2.1
1.7
1.5
ns
t
PHL
/t
PLH
Propagation delay
LE to Yn;
CP to Yn
V
CC
= 1.8 V
V
CC
= 2.5 V
V
CC
= 3.3 V
2.2
1.9
1.7
ns
C
I
Input capacitance 3.8 pF
p
p
p
Outputs enabled 25
p
PD
I
=
CC
Output disabled 6
NOTE:
1. C
PD
is used to determine the dynamic power dissipation (P
D
in µW):
P
D
= C
PD
× V
CC
2
× f
i
+ S (C
L
× V
CC
2
× f
o
) where: f
i
= input frequency in MHz; C
L
= output load capacitance in pF;
f
o
= output frequency in MHz; V
CC
= supply voltage in V; S (C
L
× V
CC
2
× f
o
) = sum of outputs.
ORDERING INFORMATION
PACKAGES
TEMPERATURE
RANGE
ORDER CODE
DRAWING
NUMBER
56-Pin Plastic 0.5 mm pitch TSSOP –40 to +85 °C 74AVC16835ADGG SOT364-1
56-Pin Plastic 0.4 mm pitch TSSOP (TVSOP) –40 to +85 °C 74AVC16835ADGV SOT481-2
