Philips Semiconductors Product data
74AVC16835A
18-bit registered driver with
Dynamic Controlled Outputs (3-State)
2002 Mar 15
7
AC WAVEFORMS FOR V
CC
= 3.0 V TO 3.6 V
RANGE
V
M
= 0.5 V
CC
V
X
= V
OL
+ 0.300 V
V
Y
= V
OH
– 0.300 V
V
OL
and V
OH
are the typical output voltage drop that occur with the
output load.
V
I
= V
CC
AC WAVEFORMS FOR V
CC
= 2.3 V TO 2.7 V AND
V
CC
< 2.3 V RANGE
V
M
= 0.5 V
CC
V
X
= V
OL
+ 0.15 V
V
Y
= V
OH
– 0.15 V
V
OL
and V
OH
are the typical output voltage drop that occur with the
output load.
V
I
= V
CC
A
n
INPUT
t
PHL
t
PLH
V
OL
V
I
GND
V
OH
Y
n
OUTPUT
SH00132
V
M
V
M
NOTE: V
M
= 0.5V
CC
at V
CC
= 2.3 to 2.7 V
Waveform 1. Input (An) to output (Yn) propagation delay
LE INPUT
Yn OUTPUT
V
I
GND
V
OH
V
OL
t
PHL
t
PLH
t
W
SH00134
V
M
V
M
V
M
NOTE: V
M
= 0.5V
CC
at V
CC
= 2.3 to 2.7V
Waveform 2. Latch enable input (LE) pulse width, the latch
enable input to output (Yn) propagation delays.
CP INPUT
Yn OUTPUT
V
I
GND
V
OH
V
OL
t
PHL
t
PLH
t
W
1/f
MAX
SH00135
V
M
V
M
V
M
NOTE: V
M
= 0.5V
CC
at V
CC
= 2.3 to 2.7 V
Waveform 3. The clock (CP) to Yn propagation delays, the
clock pulse width and the maximum clock frequency.
An
INPUT
LE
INPUT
t
SU
th
NOTE: The shaded areas indicate when the input is permitted to change
for predictable output performance.
t
SU
th
V
I
GND
V
I
GND
SH00133
V
M
V
M
V
M
= 0.5V
CC
at V
CC
= 2.3 to 2.7V
Waveform 4. Data set-up and hold times for the An input to the
LE input
V
I
GND
An INPUT
V
I
GND
V
OH
Yn OUTPUT
V
OL
CP INPUT
t
su
t
h
t
su
t
h
NOTE: The shaded areas indicate when the input is permitted to change
for predictable output performance.
SH00136
V
M
V
M
V
M
= 0.5V
CC
at V
CC
= 2.3 to 2.7 V
Waveform 5. Data set-up and hold times for the An input to the
clock CP input
t
PLZ
t
PZL
V
I
nOE INPUT
GND
V
CC
OUTPUT
LOW-to-OFF
OFF-to-LOW
V
OL
V
OH
OUTPUT
HIGH-to-OFF
OFF-to-HIGH
GND
outputs
enabled
outputs
enabled
outputs
disabled
t
PHZ
V
M
V
M
V
M
t
PZH
V
X
V
Y
SH00137
NOTE: V
M
= 0.5V
CC
at V
CC
= 2.3 to 2.7 V
Waveform 6. 3-State enable and disable times
