Data Sheet ADuM4135
Rev. B | Page 9 of 17
TYPICAL PERFORMANACE CHARACTERISTICS
CH1 520mV
2
1
13082-004
CH2 5.0VCH1 2.0V M 100ns
10.0GSPS 20.0ps/pt
A
B
W
B
W
CH1 = V
I
+ (2V/DIV)
CH2 = V
GATE
(2V/DIV)
Figure 4. Typical Input to Output Waveform, 2 nF Load,
5.1 Series Gate Resistor, V
DD1
= +5 V, V
DD2
= +15 V, V
SS2
= 5 V
2
1
13082-005
CH1 520mVCH2
5.0VCH1 2.0V M 100ns
10.0GSPS 20.0ps/pt
A
B
W
B
W
CH1 = V
I
+ (2V/DIV)
CH2 = V
GATE
(5V/DIV)
Figure 5. Typical Input to Output Waveform, 2 nF Load,
5.1 Series Gate Resistor, V
DD1
= 5 V, V
DD2
= 15 V, V
SS2
= 0 V
2
1
13082-006
CH1 960mVCH2 5.0VCH1 2.0V M 100ns
10.0GSPS 20.0ps/pt
A
B
W
B
W
CH1 = V
I
+ (2V/DIV)
CH2 = V
GATE
(5V/DIV)
Figure 6. Typical Input to Output Waveform, 2 nF Load,
3.9 Series Gate Resistor, V
DD1
= +5 V, V
DD2
= +15 V, V
SS2
= −5 V
2
1
13082-007
CH1 960mV
CH2
5.0VCH1 2.0V M 100ns
10.0GSPS 20.0ps/pt
A
B
W
B
W
CH1 = V
I
+ (2V/DIV)
CH2 = V
GATE
(5V/DIV)
Figure 7. Typical Input to Output Waveform, 2 nF Load,
3.9 Series Gate Resistor, V
DD1
= 5 V, V
DD2
= 15 V, V
SS2
= 0 V
13082-008
FREQUENCY (Hz)
0
0.5
200k
400k 600k 800k 1M0
1.0
1.5
2.0
2.5
3.0
3.5
4.0
I
DD1
(mA)
V
DD1
= 2.3V
V
DD1
= 5.0V
V
DD1
= 3.3V
Figure 8. Typical I
DD1
Current vs. Frequency, Duty = 50%, V
I
+ = V
DD1
13082-009
FREQUENCY (Hz)
200k 400k 600k 800k 1M0
I
DD2
(mA)
0
10
20
30
40
50
60
V
DD2
= 20V
V
DD2
= 15V
V
DD2
= 12V
Figure 9. Typical I
DD2
Current vs. Frequency, Duty = 50%, 2 nF Load, V
SS2
= 0 V
ADuM4135 Data Sheet
Rev. B | Page 10 of 17
2
3
1
13082-010
CH3 6.0V
CH2 5.0VCH1 5.0V M 10.0µs
1.0GSPS 1.0ns/pt
A
B
W
CH3 10.0V
B
W
B
W
CH3 = V
DD2
(10V/DIV)
CH2 = V
GATE
(5V/DIV)
CH1 = V
I
+ (5V/DIV)
Figure 10. Typical V
DD2
Startup to Output Valid
13082-011
PROPAGATION DELAY (ns)
V
DD2
(V)
10
1
2 17 22 2
7
0
20
30
40
50
60
70
80
t
D
LH
t
DH
L
Figure 11. Typical Propagation Delay vs. Output Supply Voltage (V
DD2
) for
V
DD2
= 15 V and V
DD1
= 5 V
13082-012
RISE/FALL TIME (ns)
V
DD2
(V)
12 17 22 27
5
0
10
15
20
25
30
t
DLH
t
DHL
Figure 12. Typical Rise/Fall Time vs. V
DD2
, V
DD2
– V
SS2
= 12 V, V
DD1
= 5 V,
2 nF Load, R
G
= 3.9
13082-013
PROPAGATION DELAY (ns)
INPUT SUPPLY VOLTAGE (V)
0
10
20
30
40
50
60
70
80
2.3 3.3 4.3 5.3
t
DLH
t
DHL
Figure 13. Typical Propagation Delay vs. Input Supply Voltage,
V
DD2
V
SS2
= 12 V
13082-014
PROPAGATION DELAY (ns)
AMBIENT TEMPERATURE (°C)
0
10
20
30
40
50
60
70
80
–40 10 60 110
t
DLH
t
DHL
Figure 14. Typical Propagation Delay vs. Ambient Temperature,
V
DD2
= 5 V, V
DD2
– V
SS2
= 12 V
2
3
4
1
13082-015
CH1 3.1VCH2 10.0VCH1 5.0V
M 200ns
5.0GSPS 200ps/pt
A
B
W
B
W
CH4 5.0VCH3 5.0V
B
W
B
W
CH1 = V
I
+ (5V/DIV)
CH2 = V
GATE
(10V/DIV)
CH4 = DESAT (5V/DIV)
CH3 = FAULT (5V/DIV)
Figure 15. Example Desaturation Event and Reporting
Data Sheet ADuM4135
Rev. B | Page 11 of 17
13082-016
R
DSON
(mΩ)
TEMPERATURE (°C)
0
100
200
300
400
500
600
700
800
–40 –20
0 20 40 60 80 100 120
SOURCE RESISTANCE
SINK RESISTANCE
Figure 16. Typical Output Resistance (R
DSON
) vs. Temperature, V
DD2
= 15 V,
250 mA Test
13082-017
R
DSON
(mΩ)
TEMPERATURE (°C)
0
100
200
300
400
500
600
700
800
–40 –20 0 20 40 60 80 100 120
SOURCE RESISTANCE
SINK RESISTANCE
Figure 17. Typical Output Resistance (R
DSON
) vs. Temperature, V
DD2
= 15 V,
1 A Test
2
3
1
13082-018
CH3 1.7V
CH2 5.0VCH1 5.0V M 500ns
200MSPS 5.0ns/pt
A
B
W
CH3 5.0V
B
W
B
W
CH1 = V
I
+ (5V/DIV)
CH2 = V
GATE
(5V/DIV)
CH3 = RESET (5V/DIV)
Figure 18. Example
RESET
to Output Valid
13082-019
PEAK OUTPUT CURRENT (A)
OUTPUT SUPPLY VOLTAGE (V)
0
1
2
3
4
5
6
7
8
9
12
14.5 17 19.5 22
24.5
PEAK SOURCE I
OUT
PEAK SINK I
OUT
Figure 19. Typical Peak Output Current vs. Output Supply Voltage,
2 Series Resistance (I
OUT
is the Current Going into/out of the Device Gate)

ADUM4135BRWZ

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Gate Drivers Isolated Half-bridge Gate Driver
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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