OMO ElectronicOMO Electronic
Expand menu
Hello, Sign inMy Account
0 Cart

ADUM4135BRWZ

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18
ADuM4135 Data Sheet
Rev. B | Page 12 of 17
APPLICATIONS INFORMATION
PCB LAYOUT
The ADuM4135 IGBT gate driver requires no external interface
circuitry for the logic interfaces. Power supply bypassing is required
at the input and output supply pins. Use a small ceramic capacitor
with a value between 0.01 µF and 0.1 µF to provide a good high
frequency bypass. On the output power supply pin, V
DD2
, it is
recommended also to add a 10 µF capacitor to provide the charge
required to drive the gate capacitance at the ADuM4135 outputs.
On the output supply pin, avoid the use of vias on the bypass
capacitor or employ multiple vias to reduce the inductance in
the bypassing. The total lead length between both ends of the
smaller capacitor and the input or output power supply pin
must not exceed 5 mm.
PROPAGATION DELAY RELATED PARAMETERS
Propagation delay describes the time it takes a logic signal to
propagate through a component. The propagation delay to a low
output can differ from the propagation delay to a high output. The
ADuM4135 specifies t
DLH
as the time between the rising input
high logic threshold (V
IH
) to the output rising 10% threshold (see
Figure 20). Likewise, the falling propagation delay (t
DHL
) is defined
as the time between the input falling logic low threshold (V
IL
) and
the output falling 90% threshold. The rise and fall times are
dependent on the loading conditions and are not included in the
propagation delay, which is the industry standard for gate drivers.
OUTPUT
INPUT
90%
10%
V
IH
V
IL
t
DLH
t
R
t
F
t
DHL
13082-020
Figure 20. Propagation Delay Parameters
Propagation delay skew refers to the maximum amount that
the propagation delay differs between multiple ADuM4135
components operating under the same temperature, input
voltage, and load conditions.
PROTECTION FEATURES
Fault Reporting
The ADuM4135 provides protection for faults that may occur
during the operation of an IGBT. The primary fault condition is
desaturation. If saturation is detected, the ADuM4135 shuts down
the gate drive and asserts
FAULT
low. The output remains disabled
until
RESET
is brought low for more than 500 ns, and is then
brought high.
FAULT
resets to high on the falling edge of
RESET
.
While
RESET
remains held low, the output remains disabled. The
RESET
pin has an internal, 300 kΩ pull-down resistor.
Desaturation Detection
Occasionally, component failures or faults occur with the
circuitry connected to the IGBT connected to the ADuM4135.
Examples include shorts in the inductor/motor windings or
shorts to power/ground buses. The resulting excess in current
flow causes the IGBT to come out of saturation. To detect this
condition and to reduce the likelihood of damage to the FET, a
threshold circuit is used on the ADuM4135. If the DESAT pin
exceeds the desaturation threshold (V
DESAT, TH
) of 9 V while the
high-side driver is on, the ADuM4135 enters the failure state
and turns the IGBT off. At this time, the
FAULT
pin is brought
low. An internal current source of 500 µA is provided, as well as
the option to boost the charging current using external current
sources or pull-up resistors. The ADuM4135 has a built-in
blanking time to prevent false triggering while the IGBT first
turns on. The time between desaturation detection and reporting
a desaturation fault to the
FAULT
pin is less than 2 µs (t
REPORT
).
Bring
RESET
low to clear the fault. There is a 500 ns debounce
(t
DEB_
RESET
) on the
RESET
pin. The time, t
DESAT_DELAY
, shown in
Figure 21, provides a 300 ns masking time that keeps the internal
switch that grounds the blanking capacitor tied low for the
initial portion of the IGBT on time.
13082-021
V
DESAT
V
DD2
V
f
9V
FAULT
V
CE
9V
< 200ns
V
GATE
DESAT
SWITCH
ONOFF OFF
V
I
+
DESAT
EVENT
ON
ON
~2µs RECOMMENDED
t
REPORT
< 2µs
t
DESAT_DELAY
= 300ns
Figure 21. Desaturation Detection Timing Diagram
Data Sheet ADuM4135
Rev. B | Page 13 of 17
For the following design example, see the schematic shown in
Figure 28 along with the waveforms in Figure 21. Under normal
operation, during IGBT off times, the voltage across the IGBT,
V
CE
, rises to the rail voltage supplied to the system. In this case,
the blocking diode shuts off, protecting the ADuM4135 from
high voltages. During the off times, the internal desaturation
switch is on, accepting the current going through the R
BLANK
resistor, which allows the C
BLANK
capacitor to remain at a low
voltage. For the first 300 ns of the IGBT on time, the DESAT
switch remains on, clamping the DESAT pin voltage low. After
the 300 ns delay time, the DESAT pin is released, and the DESAT
pin is allowed to rise towards V
DD2
either by the internal current
source on the DESAT pin, or additionally with an optional external
pull-up, R
BLANK
, to increase the current drive if it is not clamped
by the collector or drain of the switch being driven. V
RDESAT
is
chosen to dampen the current at this time, usually selected around
100 Ω to 2 kΩ. Select the blocking diode to block above the
high rail voltage on the collector of the IGBT and to be a fast
recovery diode.
In the case of a desaturation event, V
CE
rises above the 9 V
threshold in the desaturation detection circuit. If no R
BLANK
resistor
is used to increase the blanking current, the voltage on the blanking
capacitor, C
BLANK
, rises at a rate of 500 µA (typical) divided by the
C
BLANK
capacitance. Depending on the IGBT specifications, a
blanking time of approximately 2 µs is a typical design choice.
When the DESAT pin rises above the 9 V threshold, a fault
registers, and within 200 ns, the gate output drives low. The
output is brought low using the N-FET fault MOSFET, which
is approximately 50 times more resistive than the internal gate
driver N-FET, to perform a soft shutdown to reduce the chance
of an overvoltage spike on the IGBT during an abrupt turn-off
event. Within 2 µs, the fault is communicated back to the primary
side
FAULT
pin. To clear the fault, a reset is required.
Miller Clamp
The ADuM4135 has an integrated Miller clamp to reduce voltage
spikes on the IGBT gate caused by the Miller capacitance during
shut-off of the IGBT. When the input gate signal calls for the IGBT
to turn off (driven low), the Miller clamp MOSFET is initially
off. When the voltage on the GATE_SENSE pin crosses the 2 V
internal voltage reference, as referenced to V
SS2
, the internal
Miller clamp latches on for the remainder of the off time of the
IGBT, creating a second low impedance current path for the gate
current to follow. The Miller clamp switch remains on until the
input drive signal changes from low to high. An example waveform
of the timings is shown in Figure 22.
ONOFF OFF
V
I
+
V
I
–
V
GATE_SENSE
V
DD2
V
SS2
2V
LATCH ON
MILLER
CLAMP
SWITCH
LATCH OFF
13082-022
Figure 22. Miller Clamp Example
Thermal Shutdown
If the internal temperature of the ADuM4135 exceeds 155°C
(typical), the device enters thermal shutdown (TSD). During
the thermal shutdown time, the READY pin is brought low
on the primary side, and the gate drive is disabled. When
TSD occurs, the device does not leave TSD until the internal
temperature drops below 125°C (typical), at which time the
READY pin returns to high, and the device exits shutdown.
Undervoltage Lockout (UVLO) Faults
UVLO faults occur when the supply voltages are below the
specified UVLO threshold values. During a UVLO event on either
the primary side or secondary side, the READY pin goes low, and
the gate drive is disabled. When the UVLO condition is removed,
the device resumes operation, and the READY pin goes high.
READY Pin
The open-drain READY pin is an output that confirms
communication between the primary to secondary sides is
active. The READY pin remains high when there are no UVLO
or TSD events present. When the READY pin is low, the IGBT
gate is driven low.
Table 11. READY Pin Logic Table
UVLO TSD READY Pin Output
No No High
Yes
No
Low
No Yes Low
Yes Yes Low
ADuM4135 Data Sheet
Rev. B | Page 14 of 17
FAULT
Pin
The open-drain
FAULT
pin is an output to communicate that a
desaturation fault has occurred. When the
FAULT
pin is low, the
IGBT gate is driven low. If a desaturation event occurs, the
RESET
pin must be driven low for at least 500 ns, then high to return
operation to the IGBT gate drive.
RESET
Pin
The
RESET
pin has an internal 300 kΩ (typical) pull-down
resistor. The
RESET
pin accepts CMOS level logic. When the
RESET
pin is held low, after a 500 ns debounce time, any faults
on the
FAULT
pin are cleared. While the
RESET
pin is held low,
the switch on V
OUT_OFF
is closed, bringing the gate voltage of the
IGBT low. When
RESET
is brought high, and no fault exists, the
device resumes operation.
13082-023
RESET
FAULT
<500ns
500ns
Figure 23.
RESET
Timing
V
I
+ and V
I
− Operation
The ADuM4135 has two drive inputs, V
I
+ and V
I
−, to control
the IGBT gate drive signals, V
OUT_ON
and V
OUT_OFF
. Both the V
I
+
and V
I
− inputs use CMOS logic level inputs. The input logic of
the V
I
+ and V
I
− pins can be controlled by either asserting the
V
I
+ pin high or the V
I
− pin low. With the V
I
− pin low, the V
I
+ pin
accepts positive logic. If V
I
+ is held high, the V
I
− pin accepts
negative logic. If a fault is asserted, transmission is blocked
until the fault is cleared by the
RESET
pin.
13082-024
V
I
+
FAULT
V
I
–
V
OUT_ON
V
OUT_OFF
2
Figure 24. V
I
+ and V
I
− Block Diagram
The minimum pulse width, PW, is the minimum period in
which the timing specifications are guaranteed.
Gate Resistance Selection
The ADuM4135 provides two output nodes for the driving of
an IGBT. The benefit of this approach is that the user can select
two different series resistances for the turn-on and turn-off of
the IGBT. It is generally desired to have the turn-off occur faster
than the turn-on. To s elect the series resistance, decide what the
maximum allowed peak current is for the IGBT. Knowing the
voltage swing on the gate, as well as the internal resistance of
the gate driver, an external resistor can be chosen.
I
PEAK
= (V
DD2
− V
SS2
)/(R
DSON_N
+ R
GOFF
)
For example, if the turn-off peak current is 4 A, with a (V
DD2
− V
SS2
)
of 18 V,
R
GOFF
= ((V
DD2
− V
SS2
) − I
PEAK
× R
DSON_N
)/I
PEAK
R
GOFF
= (18 V − 4 A × 0.6 Ω)/4 A = 3.9 Ω
After R
GOFF
is selected, a slightly larger R
GON
can be selected to
arrive at a slower turn-on time.
POWER DISSIPATION
During the driving of an IGBT gate, the driver must dissipate
power. This power is not insignificant and can lead to TSD if
considerations are not made. The gate of an IGBT can be roughly
simulated as a capacitive load. Due to Miller capacitance and other
nonlinearities, it is common practice to take the stated input
capacitance, C
ISS
, of a given IGBT, and multiply it by a factor of
5 to arrive at a conservative estimate to approximate the load being
driven. With this value, the estimated total power dissipation in the
system due to switching action is given by
P
DISS
= C
EST
× (V
DD2
− V
SS2
)
2
× f
S
where:
C
EST
= C
ISS
× 5.
f
S
is the switching frequency of the IGBT.
This power dissipation is shared between the internal on
resistances of the internal gate driver switches and the external
gate resistances, R
GON
and R
GOFF
. The ratio of the internal gate
resistances to the total series resistance allows the calculation of
losses seen within the ADuM4135 chip.
P
DISS_ADuM4135
= P
DISS
× 0.5(R
DSON_P
/(R
GON
+ R
DSON_P
) +
R
DSON_N
/(R
GOFF
+ R
DSON_N
))
Tak ing t he power dissipation found inside the chip and
multiplying it by the θ
JA
gives the rise above ambient temperature
that the ADuM4135 experiences.
T
ADuM4135
= θ
JA
× P
DISS_ADuM4135
+ T
AMB
For the device to remain within specification, T
ADUM4135
must
not exceed 125°C. If T
ADuM4135
exceeds 155°C (typical), the
device enters thermal shutdown.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18

ADUM4135BRWZ

Mfr. #:
Buy ADUM4135BRWZ
Manufacturer:
Analog Devices Inc.
Description:
Gate Drivers Isolated Half-bridge Gate Driver
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet