REV. A
AD7677
–12–
The Warp Mode allows the fastest conversion rate up to 1 MSPS.
However, in this mode, and this mode only, the full specified accu-
racy is guaranteed only when the time between conversion does
not exceed 1 ms. If the time between two consecutive conversions
is longer than 1 ms, for instance, after power-up, the first conver-
sion result should be ignored. This mode makes the AD7677
ideal for applications where fast sample rates are required.
The Normal Mode is the fastest mode (800 kSPS) without any
limitation about the time between conversions. This mode makes
the AD7677 ideal for asynchronous applications such as data
acquisition systems, where both high accuracy and fast sample
rate are required.
The Impulse Mode, the lowest power dissipation mode, allows
power saving between conversions. The maximum throughput
in this mode is 666 kSPS. When operating at 100 SPS, for
example, it typically consumes only 15 µW. This feature makes
the AD7677 ideal for battery-powered applications.
Transfer Functions
Using the OB/2C digital input, the AD7677 offers two output
codings: straight binary and two’s complement. The ideal trans-
fer characteristic for the AD7677 is shown in Figure 4.
000...000
000...001
000...010
111...101
111...110
111...111
ANALOG INPUT
+FS – 1.5 LSB
+FS – 1 LSB
–FS + 1 LSB–FS
–FS + 0.5 LSB
ADC CODE – Straight Binary
Figure 4. ADC Ideal Transfer Function
TYPICAL CONNECTION DIAGRAM
Figure 5 shows a typical connection diagram for the AD7677.
Different circuitry shown on this diagram is optional and is
discussed below.
Analog Inputs
Figure 6 shows a simplified analog input section of AD7677.
AV DD AGND DGND
DVDD
OVDD OGND
SER/PAR
CNVST
BUSY
SDOUT
SCLK
RD
CS
RESET
PD
REFGND
C
REF
2.5V REF
NOTE 1
REF
100
D
CLOCK
AD7677
C/P/DSP
SERIAL PORT
DIGITAL SUPPLY
(3.3V OR 5V)
ANALOG
SUPPLY
(5V)
DVDD
OB/2C
NOTE 7
BYTESWAP
DVDD
50k
100nF
1M
IN+
ANALOG INPUT+
C
C
2.7nF
U1
NOTE 4
NOTE 5
50
AD8021
+
15
NOTE 2
NOTE 3
NOTE 6
ADR421
10F
100nF
+
10F 100nF
+
100nF
+
10F
IN–
ANALOG INPUT–
C
C
2.7nF
U2
NOTE 4
NOTE 5
50
AD8021
+
15
50
+
1F
NOTES
1. SEE VOLTAGE REFERENCE INPUT SECTION.
2. WITH THE RECOMMENDED VOLTAGE REFERENCES, C
REF
IS 47F. SEE CHAPTER VOLTAGE REFERENCE INPUT SECTION.
3. OPTIONAL CIRCUITRY FOR HARDWARE GAIN CALIBRATION.
4. THE AD8021 IS RECOMMENDED. SEE DRIVER AMPLIFIER CHOICE SECTION.
5. SEE ANALOG INPUT SECTION.
6. OPTION, SEE POWER SUPPLY SECTION.
7. OPTIONAL LOW JITTER CNVST, SEE CONVERSION CONTROL SECTION.
Figure 5. Typical Connection Diagram
REV. A
AD7677
–13–
IN+
IN–
AGND
AV DD
R+ = 168
C
S
C
S
R– = 168
Figure 6. Simplified Analog Input
The diodes shown in Figure 6 provide ESD protection for the
inputs. Care must be taken to ensure that the analog input sig-
nal never exceeds the absolute ratings on these inputs. This will
cause these diodes to become forward-biased and start conduct-
ing current. These diodes can handle a forward-biased current
of 120 mA maximum. This condition could eventually occur
when the input buffer’s (U1) or (U2) supplies are different from
AVDD. In such case, an input buffer with a short-circuit current
limitation can be used to protect the part.
This analog input structure is a true differential structure. By
using these differential inputs, signals common to both inputs
are rejected as shown in Figure 7, which represents the typical
CMRR over frequency.
FREQUENCY – Hz
90
CMRR – dB
45
75
10k 10M1k 1M
80
65
100k
55
85
70
60
50
Figure 7. Analog Input CMRR vs. Frequency
During the acquisition phase, for ac signals, the AD7677 behaves
like a one-pole RC filter consisting of the equivalent resis-
tance R+ , R–, and C
S
. The resistors R+ and R– are typically
168 V and are lumped components made up of some serial
resistors and the on resistance of the switches. The capacitor C
S
is
typically 60 pF and is mainly the ADC sampling capacitor. This
one-pole filter with a typical –3 dB cutoff frequency of 15.8 MHz
reduces undesirable aliasing effect and limits the noise com-
ing from the inputs.
Because the input impedance of the AD7677 is very high, the
AD7677 can be driven directly by a low impedance source
without gain error. That allows the user to input, as shown in
Figure 5, an external one-pole RC filter between the output of
the amplifier output and the ADC analog inputs to even further
improve the noise filtering done by the AD7677 analog input
circuit. However, the source impedance has to be kept low
because it affects the ac performances, especially the total har-
monic distortion. The maximum source impedance depends
on the amount of total harmonic distortion (THD) that can
be tolerated. The THD degrades proportionally to the source
impedance.
Single to Differential Driver
For applications using unipolar analog signals, a single-ended-
to-differential driver will allow for a differential input into the
part. The schematic is shown in Figure 8.
U2
590
590
2.5V REF
C
C
AD8021
590
AD7677
IN+
IN–
REF
2.5V REF
U1
ANALOG INPUT
(UNIPOLAR)
C
C
AD8021
590
Figure 8. Single-Ended-to-Differential Driver Circuit
This configuration, when provided an input signal of 0 to V
REF
,
will produce a differential ±2.5 V with midscale at 1.25 V.
If the application can tolerate more noise, the AD8138 can
be used.
Driver Amplifier Choice
Although the AD7677 is easy to drive, the driver amplifier needs
to meet at least the following requirements:
The driver amplifier and the AD7677 analog input circuit
have to be able together to settle for a full-scale step of the
capacitor array at a 16-bit level (0.0015%). In the amplifier’s
data sheet, the settling at 0.1% or 0.01% is more commonly
specified. It could significantly differ from the settling time at
a 16-bit level and, therefore, it should be verified prior to the
driver selection. The tiny op-amp, AD8021, which combines
ultralow noise and a high gain bandwidth, meets this settling
time requirement even when used with a high gain up to 13.
The noise generated by the driver amplifier needs to be kept
as low as possible in order to preserve the SNR and transi-
tion noise performance of the AD7677. The noise coming
from the driver is filtered by the AD7677 analog input circuit
one-pole, low-pass filter made by R+,
R–, and C
S
. The SNR
degradation due to the amplifier is:
SNR LOG
fNe
LOSS
dB N
=
+
()
20
28
784
4
3
2
π
where
f
–3 dB
is the –3 dB input bandwidth in MHz of the AD7677
(15.8 MHz) or the cutoff frequency of the input filter if
any used.
N is the noise factor of the amplifiers (1 if in buffer con-
figuration).
e
N
is the equivalent input noise voltage of each opamp in
nV/(Hz)
1/2
.
REV. A
AD7677
–14–
For instance, a driver with an equivalent input noise of 2 nV/Hz
(like the AD8021) and configured as a buffer, thus with a noise
gain of +1, the SNR degrades by only 0.07 dB with the filter in
Figure 5, and 0.27 dB without.
The driver needs to have a THD performance suitable to
that of the AD7677.
The AD8021 meets these requirements and is usually appropri-
ate for almost all applications. The AD8021 needs an external
compensation capacitor of 10 pF. This capacitor should have
good linearity as an NPO ceramic or mica type.
The AD8022 could also be used where a dual version is needed
and gain of 1 is used.
The AD8132 or the AD8138 could also be used to generate a
differential signal from a single-ended signal.
The AD829 is another alternative where high frequency (above
1 MHz) performance is not required. In gain of 1, it requires an
82 pF compensation capacitor.
The AD8610 is also another option where low bias current is
needed in low frequency applications.
Voltage Reference Input
The AD7677 uses an external 2.5 V voltage reference. The
voltage reference input REF of the AD7677 has a dynamic
input impedance. Therefore, it should be driven by a low
impedance source with an efficient decoupling between REF
and REFGND inputs. This decoupling depends on the choice
of the voltage reference, but usually consists of a 1 µF ceramic
capacitor and a low ESR tantalum capacitor connected to the
REF and REFGND inputs with minimum parasitic inductance.
47 µF is an appropriate value for the tantalum capacitor when
used with one of the recommended reference voltages:
The low noise, low temperature drift ADR421 and AD780
voltage references
The low power ADR291 voltage reference
The low cost AD1582 voltage reference
For applications using multiple AD7677s, it is more effective
to buffer the reference voltage with a low noise, very stable op
amp like the AD8031.
Care should also be taken with the reference temperature coeffi-
cient of the voltage reference, which directly affects the full-scale
accuracy if this parameter matters. For instance, a ±15 ppm/°C
tempco of the reference changes the full scale by ±1 LSB/°C.
Note that V
REF
, as mentioned in the specification table, could be
increased to AVDD – 1.85 V. Since the input range is defined
in terms of V
REF
, this would essentially increase the range to
make it a ±3 V input range with a reference voltage of 3 V. One
of the benefits here is the increased SNR obtained as a result of
this increase. The theoretical improvement as a result of this
increase in reference is 1.58 dB (20 log [3/2.5]). Due to the
theoretical quantization noise however, the observed improve-
ment is approximately 1 dB. The AD780 can be selected with a
3 V reference voltage.
FREQUENCY – Hz
75
PSRR – dB
35
65
10k 10M1k 1M
55
100k
45
70
60
50
40
Figure 9. PSRR vs. Frequency
Power Supply
The AD7677 uses three sets of power supply pins: an analog
5V supply AVDD, a digital 5 V core supply DVDD, and a
digital input/output interface supply OVDD. The OVDD supply
allows direct interface with any logic working between 2.7 V and
DVDD +0.3 V. To reduce the number of supplies needed, the
digital core (DVDD) can be supplied through a simple RC
filter from the analog supply as shown in Figure 5. The
AD7677 is independent of power supply sequencing once
OVDD does not exceed DVDD by more than 0.3 V, and thus
is free from supply voltage induced latchup. Additionally, it is
very insensitive to power supply variations over a wide fre-
quency range as shown in Figure 9.
POWER DISSIPATION
In Impulse Mode, the AD7677 automatically reduces its power
consumption at the end of each conversion phase. During the
acquisition phase, the operating currents are very low, which
allows a significant power saving when the conversion rate is
reduced as shown in Figure 10. This feature makes the AD7677
ideal for very low power battery applications.
It should be noted that the digital interface remains active even
during the acquisition phase. To reduce the operating digital
supply currents even further, the digital inputs need to be driven
close to the power rails (i.e., DVDD and DGND) and OVDD
should not exceed DVDD by more than 0.3 V.
SAMPLING RATE – SPS
1M
POWER DISSIPATION – W
0.1
10k
100 100k10 10k
100
1k
1
100k
1k
10
1M
WARP/NORMAL
IMPULSE
Figure 10. Power Dissipation vs. Sample Rate

AD7677ASTZ

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Analog to Digital Converters - ADC 57BkSPS 16-bit 1LSB INL Differential ADC
Lifecycle:
New from this manufacturer.
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