REV. A
AD7677
–15–
CONVERSION CONTROL
Figure 11 shows the detailed timing diagrams of the conversion
process. The AD7677 is controlled by the signal CNVST, which
initiates conversion. Once initiated, it cannot be restarted or
aborted, even by the power-down input PD, until the conver-
sion is complete. The CNVST signal operates independently of
CS and RD signals.
In Impulse Mode, conversions can be automatically initiated. If
CNVST is held low when BUSY is low, the AD7677 controls
the acquisition phase and then automatically initiates a new
conversion. By keeping CNVST low, the AD7677 keeps the
conversion process running by itself. It should be noted that the
analog input has to be settled when BUSY goes low. Also, at
power-up, CNVST should be brought low once to initiate the
conversion process. In this mode, the AD7677 could sometimes
run slightly faster than the guaranteed limits in the Impulse
Mode of 666 kSPS. This feature does not exist in warp or
Normal modes.
CNVST
t
1
t
2
MODE ACQUIRE CONVERT ACQUIRE CONVERT
t
7
t
8
BUSY
t
4
t
3
t
5
t
6
Figure 11. Basic Conversion Timing
Although CNVST is a digital signal, it should be designed with
this special care with fast, clean edges and levels, with minimum
overshoot and undershoot or ringing.
For applications where the SNR is critical, the CNVST signal
should have a very low jitter. Some solutions to achieve that are to
use a dedicated oscillator for CNVST generation or, at least, to
clock it with a high frequency low jitter clock as shown in Figure 5.
t
9
RESET
DATA
BUSY
CNVST
t
8
Figure 12. RESET Timing
DIGITAL INTERFACE
The AD7677 has a versatile digital interface; it can be interfaced
with the host system by using either a serial or parallel interface.
The serial interface is multiplexed on the parallel databus. The
AD7677 digital interface also accommodates both 3 V or 5 V
logic by simply connecting the OVDD supply pin of the AD7677
to the host system interface digital supply. Finally, by using the
OB/2C input pin, both two’s complement or straight binary
coding can be used.
The two signals, CS and RD, control the interface. When at least
one of these signals is high, the interface outputs are in high
impedance. Usually, CS allows the selection of each AD7677 in
multicircuits applications and is held low in a single AD7677
design. RD is generally used to enable the conversion result on
the databus.
CNVST
BUSY
DATA
BUS
CS = RD = 0
PREVIOUS CONVERSION DATA NEW DATA
t
1
t
10
t
4
t
3
t
11
Figure 13. Master Parallel Data Timing for Reading
(Continuous Read)
PARALLEL INTERFACE
The AD7677 is configured to use the parallel interface (Figure 13)
when the SER/PAR is held low. The data can either be read
after each conversion, which is during the next acquisition phase,
or during the following conversion as shown, respectively, in
Figure 14 and Figure 15. When the data is read during the conver-
sion however, it is recommended that it is a read-only during
the first half of the conversion phase. This avoids any potential
feedthrough between voltage transients on the digital interface
and the most critical analog conversion circuitry.
DATA
BUS
t
12
t
13
BUSY
CS
RD
CURRENT
CONVERSION
Figure 14. Slave Parallel Data Timing for Reading (Read
After Convert)
CS = 0
CNVST,
RD
t
1
PREVIOUS
CONVERSION
DATA
BUS
t
12
t
13
BUSY
t
4
t
3
Figure 15. Slave Parallel Data Timing for Reading (Read
During Convert)
