AX5243-1-TA05 Datasheet AX5243-1-TW30, AX5243-1-TA05 | P16-P18

AX5243

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CIRCUIT DESCRIPTION

The AX5243 is a true single chip ultra−low power

narrow−band CMOS transceiver for use in licensed and

unlicensed bands from 27 and 1050 MHz. The on−chip

transceiver consists of a fully integrated RF front−end with

modulator, and demodulator. Base band data processing is

implemented in an advanced and flexible communication

controller that enables user friendly communication via the

SPI interface.

AX5243 can be operated from a 1.8 V to 3.6 V power

supply over a temperature range of −40°C to 85°C. It

consumes 7 − 48 mA for transmitting at 868 MHz carrier

frequency, 4 – 51 mA for transmitting at 169 MHz

depending on the output power. In receive operation

AX5243 consumes 9 − 11 mA at 868 MHz carrier frequency

and 6.5 − 8.5 mA at 169 MHz.

The AX5243 features make it an ideal interface for

integration into various battery powered solutions such as

ticketing or as transceiver for telemetric applications e.g. in

sensors. As primary application, the transceiver is intended

for UHF radio equipment in accordance with the European

Telecommunication Standard Institute (ETSI) specification

EN 300 220−1 and the US Federal Communications

Commission (FCC) standard Title 47 CFR Part 15 as well as

Part 90. AX5243 is compliant with respective narrow−band

regulations. Additionally AX5243 is suited for systems

targeting compliance with Wireless M−Bus standard EN

13757−4:2005. Wireless M−Bus frame support (S, T, R) is

built−in.

AX5243 supports any data rate from 0.1 kbps to 125 kbps

for FSK, 4−FSK, GFSK, GMSK, MSK, ASK and PSK. To

achieve optimum performance for specific data rates and

modulation schemes several register settings to configure

the AX5243 are necessary, for details see the AX−RadioLab

Software which calculates the necessary register settings

and the AX5243 Programming Manual.

The AX5243 can be operated in two fundamentally

different modes.

Data is sent and received via the SPI port in frames. Pre−

and post−ambles as well as checksums can be generated

automatically. Interrupts control the data flow between a

micro−controller and the AX5243.

Both transmit and receive use frame mode. In both cases

the AX5243 behaves as a SPI slave interface. Configuration

of the AX5243 is always done via the SPI interface.

The receiver and the transmitter support multi−channel

operation for all data rates and modulation schemes.

Voltage Regulators

The AX5243 uses an on−chip voltage regulator system to

create stable supply voltages for the internal circuitry from

the primary supply VDD_IO. The I/O level of the digital

pins is VDD_IO.

Pins VDD_ANA are supplied for external decoupling of

the power supply used for the on−chip PA.

The voltage regulator system must be set into the

appropriate state before receive or transmit operations can

be initiated. This is handled automatically when

programming the device modes via the PWRMODE

to check if the regulated voltages are ready (bit SVIO) or if

VDD_IO has dropped below the brown−out level of 1.3 V

(bit SSUM).

In power−down mode the core supply voltages for digital

and analog functions are switched off to minimize leakage

power. Most register contents are preserved but access to the

FIFO is not possible and FIFO contents are lost. SPI access

to registers is possible, but at lower speed.

In deep−sleep mode all supply voltages are switched off.

All digital and analog functions are disabled. All register

contents are lost. To leave deep−sleep mode the pin SEL has

to be pulled low. This will initiate startup and reset of the

AX5243. Then the MISO line should be polled, as it will be

held low during initialization and will rise to high at the end

of the initialization, when the chip becomes ready for

operation.

Crystal Oscillator and TCXO Interface

The AX5243 is normally operated with an external

TCXO, which is required by most narrow−band regulation

with a tolerance of 0.5 ppm to 1.5 ppm depending on the

regulation. The on−chip crystal oscillator allows the use of

an inexpensive quartz crystal as the RF generation

subsystem’s timing reference when possible from a

regulatory point of view.

A wide range of crystal frequencies can be handled by the

crystal oscillator circuit. As the reference frequency impacts

both the spectral performance of the transmitter as well as

the current consumption of the receiver, the choice of

reference frequency should be made according to the

regulatory regime targeted by the application. For

guidelines see the separate Application Notes for usage of

AX5243 in compliance with various regulatory regimes.

The crystal or TCXO reference frequency should be

chosen so that the RF carrier frequency is not an integer

multiple of the crystal or TCXO frequency.

The oscillator circuit is enabled by programming the

PWRMODE register. At power−up it is enabled.

To adjust the circuit’s characteristics to the quartz crystal

being used, without using additional external components,

the tuning capacitance of the crystal oscillator can be

programmed. The transconductance of the oscillator is

automatically regulated, to allow for fastest start−up times

together with lowest power operation during steady−state

oscillation.

The integrated programmable tuning capacitor bank

makes it possible to connect the oscillator directly to pins

CLK16N and CLK16P without the need for external

AX5243

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capacitors. It is programmed using bits XTALCAP[5:0] in

To synchronize the receiver frequency to a carrier signal,

the oscillator frequency could be tuned using the capacitor

bank however, the recommended method to implement

frequency synchronization is to make use of the high

resolution RF frequency generation sub−system together

with the Automatic Frequency Control, both are described

further down.

Alternatively a single ended reference (TXCO, CXO)

may be used. For detailed TCXO network recommendations

depending on TCXO output swing refer to the AX5243

Application Note: Use with a TCXO Reference Clock.

Low Power Oscillator and Wake−on−Radio (WOR)

Mode

The AX5243 features an internal lowest power fully

integrated oscillator. In default mode the frequency of

oscillation is 640 Hz ± 1.5%, in fast mode it is 10.2 kHz

± 1.5%. These accuracies are reached after the internal

hardware has been used to calibrate the low power oscillator

versus the RF reference clock. This procedure can be run in

the background during transmit or receive operations.

The low power oscillator makes a WOR mode with a

power consumption of 500 nA possible.

If Wake−on−Radio Mode is enabled, the receiver wakes

up periodically at a user selectable interval, and checks for

a radio signal on the selected channel. If no signal is

detected, the receiver shuts down again. If a radio signal is

detected, and a valid packet is received, the microcontroller

is alerted by asserting an interrupt.

The AX5243 can thus autonomously poll for radio

signals, while the micro−controller can stay powered down,

and only wakes up once a valid packet is received. This

allows for very low average receiver power, at the expense

of longer preambles at the transmitter.

GPIO Pin

Pins SYSCLK, IRQ and TCXO_EN can be used as

general purpose I/O pins by programming pin configuration

registers PINFUNCSYSCLK, PINFUNCIRQ,

PINFUNCPWRAMP. Pin input values can be read via

programmed to the GPIO pin.

Figure 5. GPIO Pin

65 kW

VDD_IO

output data

input data

enable weak pull−up

enable output

AX5243

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SYSCLK Output

The SYSCLK pin outputs either the reference clock signal

divided by a programmable power of two or the low power

oscillator clock. Division ratios from 1 to 1024 are possible.

For divider ratios > 1 the duty cycle is 50%. Bits

SYSCLK[4:0] in the PINFUNCSYSCLK register set the

divider ratio. The SYSCLK output can be disabled.

After power−up SYSCLK outputs 1/16 of the crystal

oscillator clock, making it possible to use this clock to boot

a micro−controller.

Power−on−Reset (POR)

AX5243 has an integrated power−on−reset block. No

external POR circuit is required.

After POR the AX5243 can be reset by first setting the SPI

SEL pin to high for at least 100 ns, then setting followed by

resetting the bit RST in the PWRMODE register.

After POR or reset all registers are set to their default

values.

RF Frequency Generation Subsystem

The RF frequency generation subsystem consists of a

fully integrated synthesizer, which multiplies the reference

frequency from the crystal oscillator to get the desired RF

frequency. The advanced architecture of the synthesizer

enables frequency resolutions of 1 Hz, as well as fast settling

times of 5 – 50 ms depending on the settings (see section AC

Characteristics). Fast settling times mean fast start−up and

fast RX/TX switching, which enables low−power system

design.

For receive operation the RF frequency is fed to the mixer,

for transmit operation to the power−amplifier.

The frequency must be programmed to the desired carrier

frequency.

The synthesizer loop bandwidth can be programmed, this

serves three purposes:

1. Start−up time optimization, start−up is faster for

higher synthesizer loop bandwidths

2. TX spectrum optimization, phase−noise at

300 kHz to 1 MHz distance from the carrier

improves with lower synthesizer loop bandwidths

3. Adaptation of the bandwidth to the data−rate. For

transmission of FSK and MSK it is required that

the synthesizer bandwidth must be in the order of

the data−rate.

VCO

An on−chip VCO converts the control voltage generated

by the charge pump and loop filter into an output frequency.

This frequency is used for transmit as well as for receive

operation. The frequency can be programmed in 1 Hz steps

in the FREQ registers. For operation in the 433 MHz band,

the RFDIV bit in the PLLVCODIV register must be

programmed.

The fully integrated VCO allows to operate the device in

the frequency ranges 800 – 1050 MHz and 400 – 525 MHz.

The carrier frequency range can be extended to 54 –

525 MHz and 27 – 262 MHz by using an appropriate

external inductor between device pins L1 and L2. The bit

VCO2INT in the PLLVCODIV register must be set high to

enter this mode.

It is also possible to use a fully external VCO by setting

bits VCO2INT = 0 and VCOSEL = 1 in the PLLVCODIV

desired RF frequency must be input at device pins L1 and

L2. The control voltage for the VCO can be output at device

pin FILT when using external filter mode. The voltage range

of this output pin is 0 – 1.8 V.

This mode of operation is recommended for special

applications where the phase noise requirements are not met

when using the fully internal VCO or the internal VCO with

external inductor.

VCO Auto−Ranging

The AX5243 has an integrated auto−ranging function,

which allows to set the correct VCO range for specific

frequency generation subsystem settings automatically.

Typically it has to be executed after power−up. The function

is initiated by setting the RNG_START bit in the

PLLRANGINGA or PLLRANGINGB register. The bit is

readable and a 0 indicates the end of the ranging process.

Setting RNG_START in the PLLRANGINGA register

ranges the frequency in FREQA, while setting

RNG_START in the PLLRANGINGB register ranges the

frequency in FREQB. The RNGERR bit indicates the

correct execution of the auto−ranging.

VCO auto−ranging works with the fully integrated VCO

and with the internal VCO with external inductor.

Loop Filter and Charge Pump

The AX5243 internal loop filter configuration together

with the charge pump current sets the synthesizer loop band

width. The internal loop−filter has three configurations that

can be programmed via the register bits FLT[1:0] in registers

PLLLOOP or PLLLOOPBOOST the charge pump current

can be programmed using register bits PLLCPI[7:0] in

registers PLLCPI or PLLCPIBOOST. Synthesizer

bandwidths are typically 50 – 500 kHz depending on the

PLLLOOP

or PLLLOOPBOOST settings, for details see

the section: AC Characteristics.

The AX5243 can be setup in such a way that when the

synthesizer is started, the settings in the registers

PLLLOOPBOOST and PLLCPIBOOST are applied first

for a programmable duration before reverting to the settings

in PLLLOOP and PLLCPI. This feature enables automated

fastest start−up.

Setting bits FLT[1:0] = 00 bypasses the internal loop filter

and the VCO control voltage is output to an external loop

filter at pin FILT. This mode of operation is recommended

for achieving lower bandwidths than with the internal loop

filter and for usage with a fully external VCO.

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AX5243-1-TA05

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Manufacturer:

ON Semiconductor

Description:

RF Transceiver RADIO TRANSCEIVER

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AX5243-1-TA05

AX5243-1-TA05

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