AX5243
www.onsemi.com
20
Table 18. REGISTERS
Register Remarks
AGCGAIN This register controls the AGC (automatic gain control) loop slopes, and thus the
speed of gain adjustments. The faster the bit−rate, the faster the AGC loop should be.
TXRATE These registers control the bit rate of the transmitter.
FSKDEV These registers control the frequency deviation of the transmitter in FSK mode. The
receiver does not explicitly need to know the frequency deviation, only the channel
filter bandwidth has to be set wide enough for the complete modulation to pass.
Encoder
The encoder is located between the Framing Unit, the
Demodulator and the Modulator. It can optionally transform
the bit−stream in the following ways:
• It can invert the bit stream.
• It can perform differential encoding. This means that a
zero is transmitted as no change in the level, and a one
is transmitted as a change in the level.
• It can perform Manchester encoding. Manchester
encoding ensures that the modulation has no DC
content and enough transitions (changes from 0 to 1 and
from 1 to 0) for the demodulator bit timing recovery to
function correctly, but does so at a doubling of the data
rate.
• It can perform spectral shaping (also know as
whitening). Spectral shaping removes DC content of
the bit stream, ensures transitions for the demodulator
bit timing recovery, and makes sure that the transmitted
spectrum does not have discrete lines even if the
transmitted data is cyclic. It does so without adding
additional bits, i.e. without changing the data rate.
Spectral Shaping uses a self synchronizing feedback
shift register.
The encoder is programmed using the register
ENCODING, details and recommendations on usage are
given in the AX5243 Programming Manual.
Framing and FIFO
Most radio systems today group data into packets. The
framing unit is responsible for converting these packets into
a bit−stream suitable for the modulator, and to extract
packets from the continuous bit−stream arriving from the
demodulator.
The Framing unit supports two different modes:
• Packet modes
• Raw modes
The micro−controller communicates with the framing
unit through a 256 byte FIFO. Data in the FIFO is organized
in Chunks. The chunk header encodes the length and what
data is contained in the payload. Chunks may contain packet
data, but also RSSI, Frequency offset, Timestamps, etc.
The AX5243 contains one FIFO. Its direction is switched
depending on whether transmit or receive mode is selected.
The FIFO can be operated in polled or interrupt driven
modes. In polled mode, the microcontroller must
periodically read the FIFO status register or the FIFO count
register to determine whether the FIFO needs servicing.
In interrupt mode EMPTY, NOT EMPTY, FULL, NOT
FULL and programmable level interrupts are provided. The
AX5243 signals interrupts by asserting (driving high) its
IRQ line. The interrupt line is level triggered, active high.
Interrupts are acknowledged by removing the cause for the
interrupt, i.e. by emptying or filling the FIFO.
Basic FIFO status (EMPTY, FULL, Overrun, Underrun,
FIFO fill level above threshold, FIFO free space above
threshold) are also provided during each SPI access on
MISO while the micro− controller shifts out the register
address on MOSI. See the SPI interface section for details.
This feature significantly reduces the number of SPI
accesses necessary during transmit and receive.
Packet Modes
The AX5243 offers different packet modes. For arbitrary
packet sizes HDLC is recommended since the flag and
bit−stuffing mechanism. The AX5243 also offers packet
modes with fixed packet length with a byte indicating the
length of the packet.
In packet modes a CRC can be computed automatically.
HDLC Mode is the main framing mode of the AX5243. In
this mode, the AX5243 performs automatic packet
delimiting, and optional packet correctness check by
inserting and checking a cyclic redundancy check (CRC)
field.
NOTE: HDLC mode follows High−Level Data Link
Control (HDLC, ISO 13239) protocol.
The packet structure is given in the following table.
Table 19. HDLC PACKET STRUCTURE
Flag Address Control Information FCS (Optional Flag)
8 bit 8 bit 8 or 16 bit Variable length, 0 or more bits in multiples of 8 16 / 32 bit 8 bit
