AX5243
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31
Table 27. CONTROL REGISTER MAP
Add Description
Bit
ResetRetDirNameAdd Description
01234567
ResetRetDirName
Baseband
188
BBTUNE RW R –––01001 – – – BB TUNE
RUN
BBTUNE(3:0) Baseband Tuning
189 BBOFFSCAP RW R –111–111 – CAP INT B(2:0) – CAP INT A(2:0) Baseband Offset
Compensation
Capacitors
MAC Layer Parameters
Packet Format
200 PKTADDRCFG RW R 001–0000 MSB FIRST CRC SKIP
FIRST
FEC SYNC
DIS
– ADDR POS(3:0) Packet Address Config
201 PKTLENCFG RW R 00000000 LEN BITS(3:0 LEN POS(3:0) Packet Length Config
202 PKTLENOFFSE
T
RW R 00000000 LEN OFFSET(7:0) Packet Length Offset
203 PKTMAXLEN RW R 00000000 MAX LEN(7:0) Packet Maximum
Length
204 PKTADDR3 RW R 00000000 ADDR(31:24) Packet Address 3
205 PKTADDR2 RW R 00000000 ADDR(23:16) Packet Address 2
206 PKTADDR1 RW R 00000000 ADDR(15:8) Packet Address 1
207 PKTADDR0 RW R 00000000 ADDR(7:0) Packet Address 0
208 PKTADDRMAS
K3
RW R 00000000 ADDRMASK(31:24) Packet Address Mask
1
209 PKTADDRMAS
K2
RW R 00000000 ADDRMASK(23:16) Packet Address Mask
0
20A PKTADDRMAS
K1
RW R 00000000 ADDRMASK(15:8) Packet Address Mask
1
20B PKTADDRMAS
K0
RW R 00000000 ADDRMASK(7:0) Packet Address Mask
0
Pattern Match
210
MATCH0PAT3 RW R 00000000 MATCH0PAT(31:24) Pattern Match Unit 0,
Pattern
211 MATCH0PAT2 RW R 00000000 MATCH0PAT(23:16) Pattern Match Unit 0,
Pattern
212 MATCH0PAT1 RW R 00000000 MATCH0PAT(15:8) Pattern Match Unit 0,
Pattern
213 MATCH0PAT0 RW R 00000000 MATCH0PAT(7:0) Pattern Match Unit 0,
Pattern
214 MATCH0LEN RW R 0––00000 MATCH0
RAW
– – MATCH0LEN Pattern Match Unit 0,
Pattern Length
215 MATCH0MIN RW R –––00000 – – – MATCH0MIN Pattern Match Unit 0,
Minimum Match
216 MATCH0MAX RW R –––11111 – – – MATCH0MAX Pattern Match Unit 0,
Maximum Match
218 MATCH1PAT1 RW R 00000000 MATCH1PAT(15:8) Pattern Match Unit 1,
Pattern
219 MATCH1PAT0 RW R 00000000 MATCH1PAT(7:0) Pattern Match Unit 1,
Pattern
21C MATCH1LEN RW R 0–––0000 MATCH1
RAW
– – – MATCH1LEN Pattern Match Unit 1,
Pattern Length
21D MATCH1MIN RW R ––––0000 – – – – MATCH1MIN Pattern Match Unit 1,
Minimum Match
21E MATCH1MAX RW R ––––1111 – – – – MATCH1MAX Pattern Match Unit 1,
Maximum Match
Packet Controller
220 TMGTXBOOST RW R 00110010 TMGTXBOOSTE TMGTXBOOSTM Transmit PLL Boost
Time
221 TMGTXSETTLE RW R 00001010 TMGTXSETTLEE TMGTXSETTLEM Transmit PLL (post
Boost) Settling Time
223 TMGRXBOOST RW R 00110010 TMGRXBOOSTE TMGRXBOOSTM Receive PLL Boost
Time
224 TMGRXSETTLE RW R 00010100 TMGRXSETTLEE TMGRXSETTLEM Receive PLL (post
Boost) Settling Time
225 TMGRXOFFSA
CQ
RW R 01110011 TMGRXOFFSACQE TMGRXOFFSACQM Receive Baseband DC
Offset Acquisition Time
226 TMGRXCOARS
EAGC
RW R 00111001 TMGRXCOARSEAGCE TMGRXCOARSEAGCM Receive Coarse AGC
Time
