Si52146
Rev. 1.4 17
13 VDD_DIFF
PWR 3.3 V power supply
14 DIFF2
O, DIF 0.7 V, 100 MHz differential clock output
15 DIFF2
O, DIF 0.7 V, 100 MHz differential clock output
16 VDD_DIFF
PWR 3.3 V power supply
17 DIFF3
O, DIF 0.7 V, 100 MHz differential clock output
18 DIFF3
O, DIF 0.7 V, 100 MHz differential clock output
19 DIFF4
O, DIF 0.7 V, 100 MHz differential clock output
20 DIFF4
O, DIF 0.7 V, 100 MHz differential clock output
21 VDD_DIFF
PWR 3.3 V power supply
22 DIFF5
O, DIF 0.7 V, 100 MHz differential clock output
23 DIFF5
O, DIF 0.7 V, 100 MHz differential clock output
24 VDD_DIFF
PWR 3.3 V power supply
25 SCLK
II
2
C compatible SCLOCK
26 SDATA
I/O I
2
C compatible SDATA
27 CKPWRGD/PDB
I, PU
Active low input for asserting power down (PDB) and disabling all
outputs (internal 100 k pull-up).
28 VDD_CORE
PWR 3.3 V power supply
29 XOUT
O 25.00 MHz crystal output, Float XOUT if using only CLKIN (clock input)
30 XIN/CLKIN
I 25.00 MHz crystal input or 3.3 V, 25 MHz clock input
31 OE_DIFF0
I,PU Active high input pin enables DIFF0 (internal 100 k pull-up).
32 OE_DIFF1
I,PU Active high input pin enables DIFF1 (internal 100 k pull-up).
33 GND GND Ground for bottom pad of the IC.
Table 7. Si52146 32-Pin QFN Descriptions (Continued)
Pin # Name Type Description
