Si52146
8 Rev. 1.4
CL: Crystal load capacitance
CLe: Actual loading seen by crystal using standard value trim capacitors
Ce: External trim capacitors
Cs: Stray capacitance (terraced)
Ci : Internal capacitance (lead frame, bond wires, etc.)
2.2. CKPWRGD/PDB (Power Down) Pin
The CKPWRGD/PDB pin is a dual-function pin. During initial power up, the pin functions as the CKPWRGD pin.
Upon the first power up, if the CKPWRGD pin is low, the outputs will be disabled, but the crystal oscillator and I
2
C
logics will be active. Once the CKPWRGD pin has been sampled high by the clock chip, the pin assumes a PDB
functionality. When the pin has assumed a PDB functionality and is pulled low, the device will be placed in power
down mode. The CKPWRGD/PDB pin is required to be driven at all times even though it has an internal 100 k
resistor.
2.3. PDB (Power Down) Assertion
The PDB pin is an asynchronous active low input used to disable all output clocks in a glitch-free manner. All
outputs will be driven low in power down mode. In power down mode, all outputs, the crystal oscillator, and the I
2
C
logic are disabled.
2.4. PDB Deassertion
When a valid rising edge on CKPWRGD/PDB pin is applied, all outputs are enabled in a glitch-free manner within
two to six output clock cycles.
2.5. OE Pin
The OE pin is an active high input used to enable and disable the output clock. To enable the output clock, the OE
pin and the I
2
C OE bit need to be a logic high. By default, the OE pin and the I
2
C OE bit are set to a logic high.
There are two methods to disable the output clock: the OE pin is pulled to a logic low, or the I
2
C OE bit is set to a
logic low. The OE pin is required to be driven at all times even though it has an internal 100 k resistor.
2.6. OE Assertion
The OE pin is an active high input used for synchronous stopping and starting the respective output clock while the
rest of the clock generator continues to function. The assertion of the OE function is achieved by pulling the OE pin
and the I
2
C OE bit high which causes the respective stopped output to resume normal operation. No short or
stretched clock pulses are produced when the clocks resume. The maximum latency from the assertion to active
outputs is no more than two to six output clock cycles.
2.7. OE Deassertion
The OE function is deasserted by pulling the pin or the I
2
C OE bit to a logic low. The corresponding output is
stopped cleanly and the final output state is driven low.
2.8. SSON Pin
The SSON pin is an active input used to enable –0.5% spread spectrum on the outputs. When sampled high,
–0.5% spread is enabled on the output clocks. When sampled low, the output clocks are non-spread.
Load Capacitance (each side)
Total Capacitance (as seen by the crystal)
Ce = 2 x CL – (Cs + Ci)
Ce1 + Cs1 + Ci1
1
+
Ce2 + Cs2 + Ci2
1
()
1
=
CLe
