Si52146
Rev. 1.4 5
Table 2. AC Electrical Specifications
Parameter Symbol Test Condition Min Typ Max Unit
Crystal
Long-term Accuracy L
ACC
Measured at V
DD
/2 differential — — 250 ppm
Clock Input
CLKIN Duty Cycle T
DC
Measured at V
DD
/2 47 — 53 %
CLKIN Rise and Fall Times T
R
/T
F
Measured between 0.2 V
DD
and
0.8 V
DD
0.5 — 4.0 V/ns
CLKIN Cycle to Cycle Jitter T
CCJ
Measured at VDD/2 — — 250 ps
CLKIN Long Term Jitter T
LTJ
Measured at VDD/2 — — 350 ps
Input High Voltage V
IH
XIN/CLKIN pin 2 — VDD+0.3 V
Input Low Voltage V
IL
XIN/CLKIN pin — — 0.8 V
Input High Current I
IH
XIN/CLKIN pin, VIN = VDD — — 35 uA
Input Low Current I
IL
XIN/CLKIN pin, 0 < VIN <0.8 –35 — — uA
DIFF at 0.7 V
Duty Cycle
T
DC
Measured at 0 V differential 45 — 55 %
Output-to-Output skew T
SKEW
Measured at 0 V differential — — 800 ps
DIFF Cycle to Cycle Jitter T
CCJ
Measured at 0 V differential — 35 50 ps
PCIe Gen 1 Pk-Pk,
Common Clock
Pk-Pk
PCIe Gen 1
030 50ps
PCIe Gen 2 Phase Jitter,
Common Clock
RMS
GEN2
10 kHz < F < 1.5 MHz 0 1.75 2.1 ps
PCIe Gen 2 Phase Jitter,
Common Clock
RMS
GEN2
1.5 MHz < F < Nyquist 0 1.75 2.0 ps
PCIe Gen 3 Phase Jitter,
Common Clock
RMS
GEN3
PLL BW of 2–4 or 2–5 MHz,
CDR = 10 MHz
00.5 0.6ps
PCIe Gen 3 Phase Jitter,
Separate Reference No
Spread, SRNS
RMS
GEN3_SRNS
PLL BW of 2–4 or 2–5 MHz,
CDR = 10 MHz
— 0.35 0.42 ps
PCIe Gen 4 Phase Jitter,
Common Clock
RMS
GEN4
PLL BW of 2–4 or 2–5 MHz,
CDR = 10 MHz
—0.5 0.6 ps
Long Term Accuracy L
ACC
Measured at 0 V differential — — 100 ppm
Rising/Falling Slew Rate T
R
/T
F
Measured differentially from
±150 mV
1— 8V/ns
Voltage High V
HIGH
— — 1.15 V
Voltage Low V
LOW
–0.3 — — V
Crossing Point Voltage at
0.7 V Swing
V
OX
300 — 550 mV
Spread Range SPR-2 Down spread — –0.5 — %
Notes:
1. Visit www.pcisig.com for complete PCIe specifications.
2. Gen 4 specifications based on the PCI-Express Base Specification 4.0 rev. 0.5.
3. Download the Silicon Labs PCIe Clock Jitter Tool at www.silabs.com/pcie-learningcenter.
