LPC2364_65_66_67_68 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 7.1 — 16 October 2013 7 of 69
NXP Semiconductors
LPC2364/65/66/67/68
Single-chip 16-bit/32-bit microcontrollers
Table 3. Pin allocation table
Pin Symbol Pin Symbol Pin Symbol Pin Symbol
Row A
1TDO 2P0[3]/RXD0 3V
DD(3V3)
4 P1[4]/ENET_TX_EN
5 P1[10]/ENET_RXD1 6 P1[16]/ENET_MDC 7 V
DD(DCDC)(3V3)
8 P0[4]/I2SRX_CLK/
RD2/CAP2[0]
9 P0[7]/I2STX_CLK/
SCK1/MAT2[1]
10 P0[9]/I2STX_SDA/
MOSI1/MAT2[3]
11 - 12 -
Row B
1TMS 2RTCK 3V
SS
4 P1[1]/ENET_TXD1
5 P1[9]/ENET_RXD0 6 P1[17]/
ENET_MDIO
7V
SS
8 P0[6]/I2SRX_SDA/
SSEL1/MAT2[0]
9 P2[0]/PWM1[1]/
TXD1/TRACECLK
10 P2[1]/PWM1[2]/
RXD1/PIPESTAT0
11 - 12 -
Row C
1TCK 2TRST
3 TDI 4 P0[2]/TXD0
5 P1[8]/ENET_CRS 6 P1[15]/
ENET_REF_CLK
7 P4[28]/MAT2[0]/
TXD3
8 P0[8]/I2STX_WS/
MISO1/MAT2[2]
9V
SS
10 V
DD(3V3)
11 - 12 -
Row D
1 P0[24]/AD0[1]/
I2SRX_WS/CAP3[1]
2 P0[25]/AD0[2]/
I2SRX_SDA/TXD3
3 P0[26]/AD0[3]/
AOUT/RXD3
4 DBGEN
5 P1[0]/ENET_TXD0 6 P1[14]/ENET_RX_ER 7 P0[5]/I2SRX_WS/
TD2/CAP2[1]
8 P2[2]/PWM1[3]/
CTS1/PIPESTAT1
9 P2[4]/PWM1[5]/
DSR1/TRACESYNC
10 P2[5]/PWM1[6]/
DTR1/TRACEPKT0
11 - 12 -
Row E
1V
SSA
2V
DDA
3VREF 4V
DD(DCDC)(3V3)
5 P0[23]/AD0[0]/
I2SRX_CLK/CAP3[0]
6 P4[29]/MAT2[1]/
RXD3
7 P2[3]/PWM1[4]/
DCD1/PIPESTAT2
8 P2[6]/PCAP1[0]/RI1/
TRACEPKT1
9 P2[7]/RD2/
RTS1/TRACEPKT2
10 P2[8]/TD2/
TXD2/TRACEPKT3
11 - 12 -
Row F
1V
SS
2 RTCX1 3 RESET 4 P1[31]/SCK1/
AD0[5]
5 P1[21]/PWM1[3]/
SSEL0
6 P0[18]/DCD1/
MOSI0/MOSI
7 P2[9]/USB_CONNECT/
RXD2/EXTIN0
8 P0[16]/RXD1/
SSEL0/SSEL
9 P0[17]/CTS1/
MISO0/MISO
10 P0[15]/TXD1/
SCK0/SCK
11 - 12 -
Row G
1 RTCX2 2 VBAT 3 XTAL2 4 P0[30]/USB_D
5 P1[25]/MAT1[1] 6 P1[29]/PCAP1[1]/
MAT0[1]
7V
SS
8 P0[21]/RI1/
MCIPWR/RD1
9 P0[20]/DTR1/
MCICMD/SCL1
10 P0[19]/DSR1/
MCICLK/SDA1
11 - 12 -
Row H
