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PCF8553DTT/AJ

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P54P55-P55
PCF8553 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 3 — 27 March 2015 37 of 55
NXP Semiconductors
PCF8553
40 × 4 LCD segment driver
[1] The I
2
C-bus interface of PCF8553 is 5 V tolerant.
Table 20. I
2
C-bus characteristics
V
DD
= 1.8 V to 5.5 V; V
SS
= 0 V; T
amb
=
40
C to +85
C; unless otherwise specified; all timing values are valid within the
operating supply voltage and T
amb
range and are referenced to V
IL
and V
IH
with an input voltage swing of V
SS
to V
DD
.
[1]
Symbol Parameter Conditions Min Typ Max Unit
Pin SCL
f
SCL
SCL clock frequency - - 400 kHz
t
LOW
LOW period of the SCL
clock
1.3 - - s
t
HIGH
HIGH period of the SCL
clock
0.6 - - s
Pin SDA
t
SU;DAT
data set-up time 100 - - ns
t
HD;DAT
data hold time 0 - - ns
Pins SCL and SDA
t
BUF
bus free time between a
STOP and START
condition
1.3 - - s
t
SU;STO
set-up time for STOP
condition
0.6 - - s
t
HD;STA
hold time (repeated)
START condition
0.6 - - s
t
SU;STA
set-up time for a repeated
START condition
0.6 - - s
t
r
rise time of both SDA and
SCL signals
f
SCL
= 400 kHz - - 0.3 s
t
f
fall time of both SDA and
SCL signals
--0.3s
C
b
capacitive load for each
bus line
--400pF
t
w(spike)
spike pulse width on the I
2
C-bus - - 50 ns
PCF8553 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 3 — 27 March 2015 38 of 55
NXP Semiconductors
PCF8553
40 × 4 LCD segment driver
Fig 26. I
2
C-bus timing waveforms
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Table 21. SPI-bus characteristics
V
DD
= 1.8 V to 5.5 V; V
SS
= 0 V; T
amb
=
40
C to +85
C; unless otherwise specified; all timing values are valid within the
operating supply voltage and T
amb
range and are referenced to V
IL
and V
IH
with an input voltage swing of V
SS
to V
DD
.
Symbol Parameter Conditions Min Typ Max Unit
Pin SCL
f
SCL
SCL clock frequency - - 5 MHz
t
LOW
LOW period of the SCL
clock
150 - - ns
t
HIGH
HIGH period of the SCL
clock
80 - - ns
t
r
rise time - - 100 ns
t
f
fall time - - 100 ns
Pin CE
t
su(CE_N)
CE_N set-up time 30 - - ns
t
h(CE_N)
CE_N hold time 10 - - ns
t
rec(CE_N)
CE_N recovery time 70 - - ns
Pin SDIO
t
su
set-up time write data 5 - - ns
t
h
hold time write data 50 - - ns
t
d(R)SDIO
SDIO read delay time C
L
= 50 pF - - 150 ns
t
dis(SDIO)
SDIO disable time no load - - 50 ns
t
t(SDI-SDO)
transition time from SDI to
SDO
write to read mode 0 - - ns
PCF8553 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 3 — 27 March 2015 39 of 55
NXP Semiconductors
PCF8553
40 × 4 LCD segment driver
16. Application information
16.1 Power-on with a slowly starting power supply
The built-in POR block acts on the rising edge of the V
DD
supply voltage. It is designed to
react to fast slopes. If the system supply starts slowly, it is recommended to initiate a
software reset immediately after power-on.
16.2 I
2
C acknowledge after power-on
If the bus does not show an acknowledge at the first access, the command should be sent
a second time.
16.3 Resistors on I/O pins
The pins A0, A1, PORE, and IFS comprise internal, latching pull-down devices, which
keep these inputs at a low potential when left open. If an input is supposed to be at logic 0
potential, this pin can be either connected to V
SS
or left open.
In case a pin is supposed to be at logic 1 potential, it must be connected to V
DD
to avoid
any cross-current during power-up. A series resistance between V
DD
and the associated
pin must not exceed 1 k to ensure proper functionality.
Fig 27. SPI-bus timing waveforms
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P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P54P55-P55

PCF8553DTT/AJ

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Manufacturer:
NXP Semiconductors
Description:
Latches 40 X 4 LCD segment driver
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