PCF8553 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 3 — 27 March 2015 8 of 55
NXP Semiconductors
PCF8553
40 × 4 LCD segment driver
In power-down mode (see Section 8.3.1)
• if pin CLK is configured as an output, there is no signal on CLK
• if pin CLK is configured as an input, the signal on CLK can be removed.
Remark: A clock signal must always be supplied to the device if the display is enabled
(see bit DE in Table 7 on page 8
). Removing the clock may freeze the LCD in a DC state,
which is not suitable for the liquid crystal.
8.2.2 Command: Display_ctrl_1
The Display_ctrl_1 command allows configuring the basic display set-up.
[1] Default value.
[2] Not applicable for static drive mode.
[3] See Section 8.3.1
.
8.2.2.1 Enhanced power drive mode
By setting the BOOST bit to logic 1, the driving capability of the display signals is
increased to cope with large displays with a higher effective capacitance. Setting this bit
increases the current consumption on V
LCD
.
8.2.2.2 Multiplex drive mode
MUX[1:0] sets the multiplex driving scheme and the associated backplane drive signals,
which are active. For further details, see Section 9.2 on page 16
.
Table 7. Display_ctrl_1 - display control command 1 register (address 02h) bit description
Bit Symbol Value Description
7 to 5 - 000 default value
4BOOST large display mode support
0
[1]
standard power drive scheme
1 enhanced power drive scheme for higher display
loads
3 to 2 MUX[1:0] multiplex drive mode selection
00
[1]
1:4 multiplex drive mode; COM0 to COM3
(n
MUX
=4)
01 1:3 multiplex drive mode; COM0 to COM2
(n
MUX
=3)
10 1:2 multiplex drive mode; COM0 and COM1
(n
MUX
=2)
11 static drive mode; COM0 (n
MUX
=1)
1B
[2]
bias mode selection
0
[1] 1
⁄
3
bias (a
bias
=2)
1
1
⁄
2
bias (a
bias
=1)
0DE display enable
[3]
0
[1]
display disabled; device is in power-down mode
1 display enabled; device is in power-on mode
