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PCF8553DTT/AJ

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P54P55-P55
PCF8553 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 3 — 27 March 2015 52 of 55
NXP Semiconductors
PCF8553
40 × 4 LCD segment driver
28. Tables
Table 1. Ordering information . . . . . . . . . . . . . . . . . . . . .2
Table 2. Ordering options . . . . . . . . . . . . . . . . . . . . . . . . .2
Table 3. Marking codes . . . . . . . . . . . . . . . . . . . . . . . . . .2
Table 4. Pin description of PCF8553DTT (TSSOP56) . .5
Table 5. Registers of the PCF8553 . . . . . . . . . . . . . . . . .6
Table 6. Device_ctrl - device control command register
(address 01h) bit description . . . . . . . . . . . . . . .7
Table 7. Display_ctrl_1 - display control command 1
register (address 02h) bit description . . . . . . . .8
Table 8. Display_ctrl_2 - display control command 2
register (address 03h) bit description . . . . . . . .9
Table 9. Software_reset - software reset command
register (address 00h) bit description . . . . . . .11
Table 10. Register to segment and backplane mapping .12
Table 11. Selection of possible display configurations . . .14
Table 12. Biasing characteristics . . . . . . . . . . . . . . . . . . .16
Table 13. I
2
C slave address byte . . . . . . . . . . . . . . . . . . .28
Table 14. R/W-bit description . . . . . . . . . . . . . . . . . . . . . .28
Table 15. Serial interface . . . . . . . . . . . . . . . . . . . . . . . . .29
Table 16. Address byte definition . . . . . . . . . . . . . . . . . . .29
Table 17. Limiting values . . . . . . . . . . . . . . . . . . . . . . . . .32
Table 18. Electrical characteristics . . . . . . . . . . . . . . . . .33
Table 19. Frequency characteristics . . . . . . . . . . . . . . . .35
Table 20. I
2
C-bus characteristics . . . . . . . . . . . . . . . . . . .37
Table 21. SPI-bus characteristics . . . . . . . . . . . . . . . . . .38
Table 22. SnPb eutectic process (from J-STD-020D) . . .42
Table 23. Lead-free process (from J-STD-020D) . . . . . .42
Table 24. Selection of LCD segment drivers . . . . . . . . . .45
Table 25. Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . .47
Table 26. Revision history . . . . . . . . . . . . . . . . . . . . . . . .49
PCF8553 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 3 — 27 March 2015 53 of 55
NXP Semiconductors
PCF8553
40 × 4 LCD segment driver
29. Figures
Fig 1. Block diagram of PCF8553 . . . . . . . . . . . . . . . . . .3
Fig 2. Pin configuration of PCF8553DTT (TSSOP56) . . .4
Fig 3. Address counter incrementing. . . . . . . . . . . . . . . .7
Fig 4. Reset pulse timing . . . . . . . . . . . . . . . . . . . . . . . .10
Fig 5. Display RAM organization bitmap for MUX 1:4 . .13
Fig 6. Example of displays suitable for PCF8553 . . . . .14
Fig 7. Typical system configuration using I
2
C-bus,
internal power-on reset enabled . . . . . . . . . . . . .15
Fig 8. Typical system configuration using SPI-bus,
internal power-on reset disabled . . . . . . . . . . . . .15
Fig 9. Electro-optical characteristic: relative
transmission curve of the liquid . . . . . . . . . . . . . .18
Fig 10. Static drive mode waveforms. . . . . . . . . . . . . . . .19
Fig 11. Waveforms for the 1:2 multiplex drive mode
with
1
⁄
2
bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Fig 12. Waveforms for the 1:2 multiplex drive mode
with
1
⁄
3
bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Fig 13. Waveforms for the 1:3 multiplex drive mode
with
1
⁄
3
bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Fig 14. Waveforms for the 1:4 multiplex drive mode
with
1
⁄
3
bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Fig 15. Recommended power-up and power-off
sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Fig 16. I
2
C read and write protocol . . . . . . . . . . . . . . . . .26
Fig 17. I
2
C read and write signaling. . . . . . . . . . . . . . . . .26
Fig 18. Data transfer overview. . . . . . . . . . . . . . . . . . . . .29
Fig 19. SPI-bus write example: writing two data bytes
to registers 00h and 01h . . . . . . . . . . . . . . . . . . .30
Fig 20. SPI-bus read example: reading two data bytes
from registers 04h and 05h . . . . . . . . . . . . . . . . .30
Fig 21. Device protection diagram. . . . . . . . . . . . . . . . . .31
Fig 22. Typical I
DD
and I
DD(LCD)
in power-down mode
as function of temperature. . . . . . . . . . . . . . . . . .34
Fig 23. Typical I
DD(LCD)
as function of display load . . . . .34
Fig 24. Typical I
DD(LCD)
as function of f
fr
. . . . . . . . . . . . . .35
Fig 25. Relation of frame frequency (f
fr
), clock
frequency (f
clk
) and multiplex-rate (n
MUX
) . . . . . .36
Fig 26. I
2
C-bus timing waveforms . . . . . . . . . . . . . . . . . .38
Fig 27. SPI-bus timing waveforms . . . . . . . . . . . . . . . . .39
Fig 28. Package outline SOT364-1 (TSSOP56)
of PCF8553DTT. . . . . . . . . . . . . . . . . . . . . . . . . .40
Fig 29. Temperature profiles for large and small
components . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
Fig 30. Footprint information for reflow soldering
of SOT364-1 (TSSOP56) of PCF8553DTT . . . . .44
PCF8553 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 3 — 27 March 2015 54 of 55
continued >>
NXP Semiconductors
PCF8553
40 × 4 LCD segment driver
30. Contents
1 General description. . . . . . . . . . . . . . . . . . . . . . 1
2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1
3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
4 Ordering information. . . . . . . . . . . . . . . . . . . . . 2
4.1 Ordering options. . . . . . . . . . . . . . . . . . . . . . . . 2
5 Marking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
6 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3
7 Pinning information. . . . . . . . . . . . . . . . . . . . . . 4
7.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
7.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5
8 Functional description . . . . . . . . . . . . . . . . . . . 6
8.1 Registers of the PCF8553 . . . . . . . . . . . . . . . . 6
8.2 Command registers of the PCF8553 . . . . . . . . 7
8.2.1 Command: Device_ctrl . . . . . . . . . . . . . . . . . . . 7
8.2.1.1 Internal oscillator and clock output . . . . . . . . . . 7
8.2.2 Command: Display_ctrl_1. . . . . . . . . . . . . . . . . 8
8.2.2.1 Enhanced power drive mode . . . . . . . . . . . . . . 8
8.2.2.2 Multiplex drive mode. . . . . . . . . . . . . . . . . . . . . 8
8.2.3 Command: Display_ctrl_2. . . . . . . . . . . . . . . . . 9
8.2.3.1 Blinking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
8.2.3.2 Line inversion
(driving scheme A)
and frame inversion
(driving scheme B) . . . . . . . . . . . . . . . . . . . . . . 9
8.3 Starting and resetting the PCF8553 . . . . . . . . 10
8.3.1 Power-down mode . . . . . . . . . . . . . . . . . . . . . 10
8.3.2 Power-On Reset
(POR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
8.3.3 Hardware reset: RST
pin . . . . . . . . . . . . . . . . 11
8.3.4 Command: Software_reset. . . . . . . . . . . . . . . 11
8.4 Display data register mapping . . . . . . . . . . . . 11
9 Possible display configurations. . . . . . . . . . . 14
9.1 LCD bias generator . . . . . . . . . . . . . . . . . . . . 16
9.2 LCD voltage selector . . . . . . . . . . . . . . . . . . . 16
9.2.1 Electro-optical performance . . . . . . . . . . . . . . 17
9.2.2 LCD drive mode waveforms . . . . . . . . . . . . . . 19
9.2.2.1 Static drive mode . . . . . . . . . . . . . . . . . . . . . . 19
9.2.2.2 1:2 Multiplex drive mode. . . . . . . . . . . . . . . . . 20
9.2.2.3 1:3 Multiplex drive mode. . . . . . . . . . . . . . . . . 22
9.2.2.4 1:4 Multiplex drive mode. . . . . . . . . . . . . . . . . 23
9.3 Backplane and segment outputs . . . . . . . . . . 24
9.3.1 Backplane outputs . . . . . . . . . . . . . . . . . . . . . 24
9.3.2 Segment outputs. . . . . . . . . . . . . . . . . . . . . . . 24
10 Power Sequencing. . . . . . . . . . . . . . . . . . . . . . 25
10.1 Power-on . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
10.2 Power-off . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
10.3 Power sequences . . . . . . . . . . . . . . . . . . . . . 25
11 Bus interfaces . . . . . . . . . . . . . . . . . . . . . . . . . 26
11.1 I
2
C-bus interface . . . . . . . . . . . . . . . . . . . . . . 26
11.1.1 Bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
11.1.2 START and STOP conditions. . . . . . . . . . . . . 27
11.1.3 Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . 27
11.1.4 I
2
C interface protocol . . . . . . . . . . . . . . . . . . . 27
11.1.4.1 Write protocol. . . . . . . . . . . . . . . . . . . . . . . . . 27
11.1.4.2 Read protocol. . . . . . . . . . . . . . . . . . . . . . . . . 28
11.1.4.3 I
2
C-bus slave address . . . . . . . . . . . . . . . . . . 28
11.2 SPI-bus interface . . . . . . . . . . . . . . . . . . . . . . 29
11.2.1 Data transmission . . . . . . . . . . . . . . . . . . . . . 29
11.2.1.1 Write protocol. . . . . . . . . . . . . . . . . . . . . . . . . 29
11.2.1.2 Read protocol. . . . . . . . . . . . . . . . . . . . . . . . . 30
11.3 EMC detection . . . . . . . . . . . . . . . . . . . . . . . . 31
12 Internal circuitry . . . . . . . . . . . . . . . . . . . . . . . 31
13 Safety notes. . . . . . . . . . . . . . . . . . . . . . . . . . . 31
14 Limiting values . . . . . . . . . . . . . . . . . . . . . . . . 32
15 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 33
16 Application information . . . . . . . . . . . . . . . . . 39
16.1 Power-on with a slowly starting power supply 39
16.2 I
2
C acknowledge after power-on . . . . . . . . . . 39
16.3 Resistors on I/O pins . . . . . . . . . . . . . . . . . . . 39
17 Package outline. . . . . . . . . . . . . . . . . . . . . . . . 40
18 Handling information . . . . . . . . . . . . . . . . . . . 41
19 Packing information . . . . . . . . . . . . . . . . . . . . 41
19.1 Tape and reel information . . . . . . . . . . . . . . . 41
20 Soldering of SMD packages. . . . . . . . . . . . . . 41
20.1 Introduction to soldering. . . . . . . . . . . . . . . . . 41
20.2 Wave and reflow soldering. . . . . . . . . . . . . . . 41
20.3 Wave soldering . . . . . . . . . . . . . . . . . . . . . . . 42
20.4 Reflow soldering . . . . . . . . . . . . . . . . . . . . . . 42
21 Footprint information . . . . . . . . . . . . . . . . . . . 44
22 Appendix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
22.1 LCD segment driver selection . . . . . . . . . . . . 45
23 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 47
24 References. . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
25 Revision history . . . . . . . . . . . . . . . . . . . . . . . 49
26 Legal information . . . . . . . . . . . . . . . . . . . . . . 50
26.1 Data sheet status. . . . . . . . . . . . . . . . . . . . . . 50
26.2 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
26.3 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 50
26.4 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 51
27 Contact information . . . . . . . . . . . . . . . . . . . . 51
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P54P55-P55

PCF8553DTT/AJ

Mfr. #:
Buy PCF8553DTT/AJ
Manufacturer:
NXP Semiconductors
Description:
Latches 40 X 4 LCD segment driver
Lifecycle:
New from this manufacturer.
Delivery:
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