RT8207LGQW Datasheet RT8207LGQW | P19-P21

DS8207L/M-08 September 2016 www.richtek.com

RT8207L/M

Figure 5. Boundary Condition of CCM/DCM

The switching waveforms may appear noisy and

asynchronous when light loading causes diode-emulation

operation, but this is a normal operating condition that

results in high light load efficiency. Trade offs in DEM

noise vs. light load efficiency is made by varying the

inductor value. Generally, low inductor values produce a

broader efficiency vs. load curve, while higher values result

in higher full load efficiency (assuming that the coil

resistance remains fixed) and less output voltage ripple.

The disadvantages for using higher inductor values include

larger physical size and degraded load transient response

(especially at low input voltage levels).

Current Limit Setting for VDDQ (CS)

The RT8207L/M provides cycle-by-cycle current limiting

control. The current limit circuit employs a unique “valley”

current sensing algorithm. If the magnitude of the current

sense signal at PHASE is above the current limit

threshold, the PWM is not allowed to initiate a new cycle

(Figure 6). The actual peak current is greater than the

current limit threshold by an amount equal to the inductor

ripple current. Therefore, the exact current limit

characteristic and maximum load capability are a function

of the sense resistance, inductor value, and battery and

output voltage.

PEAK

LIM

LOAD

Figure 6. “Valley” Current Limit

The RT8207L/M uses the on resistance of the synchronous

rectifier as the current sense element and supports

temperature compensated MOSFET R

DS(ON)

sensing. The

setting resistor, R

ILIM

, between the CS pin and VDD sets

the current limit threshold, and the recommended value

is greater than 5kΩ. The CS pin sinks an internal 10μA

(typ.) current source at room temperature. This current

has a 4700ppm/°C temperature slope to compensate the

temperature dependency of R

DS(ON)

. When the voltage

drop across the low side MOSFET equals the voltage

across the R

ILIM

setting resistor, the positive current limit

will activate. The high side MOSFET will not be turned on

until the voltage drop across the low side MOSFET falls

below the current limit threshold.

Choose a current limit setting resistor via the following

equation :



ILIM LIMIT DS(ON)

RI x R /10μ

Carefully observe the PCB layout guidelines to ensure

that noise and DC errors do not corrupt the current-sense

signal seen by PHASE and PGND.

Current Protection for VTT

The LDO has an internally fixed constant over current

limiting of 2.6A while operating at normal condition. After

the first time VTT voltage comes to within 15% of its set

voltage, this over current point is reduced to 1.3A. From

then on, when the output voltage goes outside 20% of its

set voltage, the internal power good signal will transit from

high to low.

MOSFET Gate Driver (UGATE, LGATE)

The high side driver is designed to drive high current, low

DS(ON)

N-MOSFET(s). When configured as a floating

driver, 5V bias voltage is delivered from the VDDP supply.

The average drive current is proportional to the gate charge

at V

= 5V times switching frequency. The instantaneous

drive current is supplied by the flying capacitor between

the BOOT and PHASE pins.

A dead time to prevent shoot through is internally

generated between high side MOSFET off to low side

MOSFET on, and low side MOSFET off to high side

MOSFET on.

Slope = (V

- V

VDDQ

) / L

PEAK

LOAD

= I

PEAK

/ 2

DS8207L/M-08 September 2016www.richtek.com

RT8207L/M

The low side driver is designed to drive high current, low

DS(ON)

N-MOSFET(s). The internal pull down transistor

that drives LGATE low is robust, with a 0.8Ω typical on

resistance. A 5V bias voltage is delivered from the VDDP

supply. The instantaneous drive current is supplied by the

flying capacitor between VDDP and PGND.

For high current applications, some combinations of high

and low side MOSFETs may cause excessive gate drain

coupling, which leads to efficiency killing, EMI producing

shoot through currents. This is often remedied by adding

a resistor in series with BOOT, which increases the turn-

on rising time of the high side MOSFET without degrading

the turn-off time (Figure 7).

BOOT

UGATE

PHASE

Figure 7. Increasing the UGATE Rise Time

Power Good Output (PGOOD)

The power good output is an open drain output that requires

a pull up resistor. When the output voltage is 15% above

or 10% below its set voltage, PGOOD gets pulled low. It

is held low until the output voltage returns to within these

tolerances once more. During soft-start, PGOOD is actively

held low and only allowed to transition high after soft-start

is over and the output reaches 93% of its set voltage.

There is a 2.5μs delay built into PGOOD circuitry to prevent

false transition.

POR Protection

The RT8207L/M has a VDDP supply power on reset

protection (POR). When the VDDP voltage is higher than

4.2V (typ.), VDDQ, VTT and VTTREF will be activated.

This is a non-latch protection.

Soft-Start

The RT8207L/M provides an internal soft-start function to

prevent large inrush current and output voltage overshoot

when the converter starts up. Soft-start (SS) automatically

begins once the chip is enabled. During soft-start, internal

current limit circuit gradually ramps up the inductor current

from zero. The maximum current-limit value is set

externally as described in previous section. The soft-start

time is determined by the current limit level and output

capacitor value. If the current limit threshold is set for

200mV, the typical soft-start duration is 3ms after S5 is

enabled.

The soft-start function of VTT is achieved by the current

limit and VTTREF voltage through the internal RC delay

ramp up after S3 is high. During VTT startup, the current

limit level is 2.6A. This allows the output to start up

smoothly and safely under enough source/sink ability.

Output Over Voltage Protection (OVP)

The output voltage can be continuously monitored for over

voltage. If the output exceeds 15% of its set voltage

threshold, over voltage protection is triggered and the

LGATE low side gate driver is forced high. This activates

the low side MOSFET switch which rapidly discharges

the output capacitor and reduces the input voltage. There

is a 5μs latch delay built into the over voltage protection

circuit. The RT8207L/M will be latched if the output voltage

remains above the OV threshold after the latch delay

period and can then only be released by VDD power on

reset or S5.

Note that latching the LGATE high will cause the output

voltage to dip slightly negative when energy has been

previously stored in the LC tank circuit. For loads that

cannot tolerate a negative voltage, place a power Schottky

diode across the output to act as a reverse polarity clamp.

If the over voltage condition is caused by a short in high

side switch, turning the low side MOSFET on 100% will

create an electrical short between the battery and GND,

hence blowing the fuse and disconnecting the battery from

the output.

Output Under Voltage Protection (UVP)

The output voltage can be continuously monitored for under

voltage. When enabled, the under voltage protection is

triggered if the output is less than 70% of its set voltage

threshold. Then, both UGATE and LGATE gate drivers will

be forced low while entering soft discharge mode. During

soft-start, the UVP has a blanking time around 5ms.

DS8207L/M-08 September 2016 www.richtek.com

RT8207L/M

Thermal Protection

The RT8207L/M monitors the temperature of itself. If the

temperature exceeds the threshold value, 165°C (typ.),

the PWM output, VTTREF and VTT will be shut off. The

RT8207L/M is latched once thermal shutdown is triggered

and can only be released by VDD power on reset or S5.

Output Voltage Setting (FB)

The RT8207L/M can be used as DDR2 (V

VDDQ

= 1.8V)

and DDR3 (V

VDDQ

= 1.5V) power supply or as an adjustable

output voltage (0.75V < V

VDDQ

< 3.3V) by connecting the

FB pin according to Table 1.

Table 1. FB and output voltage setting

FB VDDQ (V)

VTTREF

and VTT

NOTE

VDD 1.8 V

VDD Q

/ 2 DDR2

GND 1.5 V

VDDQ

/2 DDR3

Resistors

Adjustable V

VDD Q

/ 2

0.75V < V

VDDQ

< 3.3V

Connect a resistive voltage divider at FB between VDDQ

and GND to adjust the respective output voltage between

0.75V and 3.3V (Figure 8). Choose R2 to be approximately

10kΩ and solve for R1 using the equation as follows :









VDDQ REF

VV x 1

where V

REF

is 0.75V (typ.).

PHASE

LGATE

VDDQ

UGATE

VDDQ

GND

Figure 8. Setting VDDQ with a Resistive Voltage Divider

VTT Linear Regulator and VTTREF

The RT8207L/M integrates a high performance low dropout

linear regulator that is capable of sourcing and sinking

currents up to 1.5A. This VTT linear regulator employs

ultimate fast response feedback loop so that small ceramic

capacitors are enough for keeping track of VTTREF within

40mV at all conditions, including fast load transient. To

achieve tight regulation with minimum effect of wiring

resistance, a remote sensing terminal, VTTSNS, should

be connected to the positive node of the VTT output

capacitor(s) as a separate trace from the VTT pin. For

stable operation, total capacitance of the VTT output

terminal can be equal to or greater than 20μF. It is

recommended to attach two 10μF ceramic capacitors in

parallel to minimize the effect of ESR and ESL. If ESR of

the output capacitor is greater than 2mΩ, insert an RC

filter between the output and VTTSNS input to achieve

loop stability. The RC filter time constant should be almost

the same or slightly lower than the time constant made

by the output capacitor and its ESR. The VTTREF block

consists of on-chip 1/2 divider, LPF and buffer. This regulator

also has sink and source capability up to 10mA. Bypass

VTTREF to GND with a 33nF ceramic capacitor for stable

operation.

VDD sources the load of VTTREF to follow half voltage of

VDDQ. If VTTREF capacitor is so large that the VTTREF

is unable to follow half VDDQ voltage at time during soft

start period, VTTREF will sink large current from VDD which

causes large voltage drop at VDDP to VDD resistor and

has the opportunity of UVLO. The following equation

provides the maximum value of VTTREF capacitor

calculation.

VDDQ

SS VTTREF

VDD

VDDQ OUT

VTTREF

VDDQ VDD IN

0.03

T = C

1.1 R 12 2

T =

0.03

R2L

0.03

C =

V1.1R12 V

0.03

R2L

















Where R

VDD

is the resistor between VDDP and VDD pin.

is the turn on resistor of low-side MOSFET. C

VTTREF

is the capacitor on the VTTREF pin. T

is the soft start

time for VDDQ at the no load condition.

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