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Table 2. S3 and S5 truth table
STATE S3 S5 VDDQ VTTREF VTT
S0 Hi Hi On On On
S3 Lo Hi On On Off (Hi-Z)
S4/S5 Lo Lo
Off
(Discharge)
Off
(Discharge)
Off
(Discharge
)
VDDQ and VTT Discharge Control
The RT8207L/M discharges VDDQ, VTTREF and VTT
outputs when S5 is low or in the S4/S5 state. There are
two different discharge modes. For the RT8207L, the
discharge mode is set by connecting the MODE pin
according to Table 3. For the RT8207M, the discharge
mode is set by placing a resistor (R
TON
) between the TON
pin and V
IN
, as shown in Table 4.
MODE Discharge Mode
VDD No discharge
VDDQ Tracking discharge
GND Non-tracking discharge
Table 3. Discharge selection for the RT8207L
TON pin connect R
TON
to Discharge Mode
V
IN
Non-tracking discharge
Table 4. Discharge selection for the RT8207M
When in tracking discharge mode, the RT8207L
discharges outputs through the internal VTT regulator
transistors and VTT output tracks half of the VDDQ voltage
during this discharge. Note that the VDDQ discharge
current flows via VLDOIN to VTTGND; thus VLDOIN must
be connected to VDDQ in this mode. The internal LDO
can handle up to 1.5A and discharge quickly. After VDDQ
is discharged down to 0.15V, the terminal LDO will be
turned off and the operation mode is changed to the non-
tracking discharge mode.
When in non-tracking discharge mode, the RT8207L/M
discharges outputs using internal MOSFETs which are
connected to VDDQ and VTT. The current capability of
these MOSFETs is limited to discharge slowly. Note that
the VDDQ discharge current flows from VDDQ to GND in
this mode.
When in no discharge mode, the RT8207L does not
discharge output charge at all.
Output Inductor Selection
The switching frequency (on-time) and operating point (%
ripple or L
IR
) determine the inductor value as follows :
ON IN VDDQ
IR LOAD(MAX)
t x (V V )
L
L x I
where L
IR
is the ratio of the peak-to-peak ripple current to
the maximum average inductor current.
Find a low loss inductor having the lowest possible DC
resistance that fits in the allotted dimensions. Ferrite cores
are often the best choice, although powdered iron is
inexpensive and can work well at 200kHz. The core must
be large enough not to saturate at the peak inductor current
(I
PEAK
) :



PEAK LOAD(MAX) IR LOAD(MAX)
I I (L /2) x I
Output Management by S3, S5 Control
In DDR2/DDR3 memory applications, it is important to
always keep VDDQ higher than VTT/VTTREF, even during
start up and shutdown. The RT8207L/M provides this
management by simply connecting both S3 and S5
terminals to the sleep-mode signals such as SLP_S3 and
SLP_S5 in notebook PC system. All VDDQ, VTTREF and
VTT are turned on at S0 state (S3 = S5 = high). In S3
state (S3 = low, S5 = high), VDDQ and VTTREF voltages
are kept on while VTT is turned off and left at high
impedance (high-Z) state. The VTT output is floated and
does not sink or source current in this state. In S4/S5
states (S3 = S5 = low), all of the three outputs are
disabled. Outputs are discharged to ground according to
the discharge mode selected by the MODE pin (see VDDQ
and VTT Discharge Control section). The code of each
state represents the following: S0 = full ON, S3 = suspend
to RAM (STR), S4 = suspend to disk (STD), S5 = soft
OFF. (See Table 2)
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This inductor ripple current also impacts transient-response
performance, especially at low V
IN
V
VDDQ
differences.
Low inductor values allow the inductor current to slew
faster, replenishing charge removed from the output filter
capacitors by a sudden load step. The peak amplitude of
the output transient (V
SAG
) is also a function of the output
transient. V
SAG
also features a function of the maximum
duty factor, which can be calculated from the on-time and
minimum off-time :
()



SAG
2
LOAD ON OFF(MIN)
OUT VDDQ IN ON VDDQ ON OFF(MIN)
V
I x L x (tt )
2 x C x V x V x t V x (t t )
where minimum off-time, t
OFF(MIN)
, is 400ns typically.
Output Capacitor Selection
The output filter capacitor must have low enough ESR to
meet output ripple and load-transient requirements, yet
have high enough ESR to satisfy stability requirements.
Also, the capacitance must be high enough to absorb the
inductor energy going from a full-load to no-load condition
without tripping the OVP circuit.
For CPU core voltage converters and other applications
where the output is subject to violent load transients, the
output capacitor's size depends on how much ESR is
needed to prevent the output from dipping too low under a
load transient. Ignoring the sag due to finite capacitance :
PP
LOAD(MAX)
V
ESR
I
In non-CPU applications, the output capacitor's size
depends on how much ESR is needed to maintain an
acceptable level of output voltage ripple :
PP
IR LOAD(MAX)
V
ESR
L x I
where V
PP
is the peak-to-peak output voltage ripple.
Organic semiconductor capacitor(s) or specialty polymer
capacitor(s) are recommended.
For low input-to-output voltage differentials (V
IN
/V
VDDQ
<
2), additional output capacitance is required to maintain
stability and good efficiency in ultrasonic mode.
2
PEAK
SOAR
OUT VDDQ
(I ) x L
V
2 x C x V
where I
PEAK
is the peak inductor current.
Output Capacitor Stability
Stability is determined by the value of the ESR zero relative
to the switching frequency. The point of instability is given
by the following equation :

SW
ESR
OUT
f
1
f
2 x x ESR x C 4
The amount of overshoot due to stored inductor energy
can be calculated as :
Do not put high value ceramic capacitors directly across
the outputs without taking precautions to ensure stability.
Large ceramic capacitors can have a high ESR zero
frequency and cause erratic, unstable operation. However,
it is easy to add enough series resistance by placing the
capacitors a couple of inches downstream from the
inductor and connecting VDDQ or the FB voltage-divider
close to the inductor.
Unstable operation manifests itself in two related and
distinctly different ways: double-pulsing and feedback loop
instability.
Double-pulsing occurs due to noise on the output or
because the ESR is so low that there is not enough voltage
ramp in the output voltage signal. This
fools the error
comparator into triggering a new cycle immediately after
the 400ns minimum off-time period has expired. Double
pulsing is more annoying than harmful, resulting in nothing
worse than increased output ripple. However, it may
indicate the possible presence of loop instability, which
is caused by insufficient ESR.
Loop instability can result in oscillations at the output in
the form of line or load perturbations, which can trip the
over voltage protection latch or cause the output voltage
to fall below the tolerance limit.
The easiest method for checking stability is to apply a
very fast zero-to-max load transient and carefully observe
the output-voltage-ripple envelope for overshoot and ringing.
It helps to simultaneously monitor the inductor current
with an AC current probe. Do not allow more than one
cycle of ringing after the initial step-response under- or
over-shoot.
24
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Figure 9. Derating Curve of Maximum Power Dissipation
Layout Considerations
Layout is very important in high frequency switching
converter design. If designed improperly, the PCB could
radiate excessive noise and contribute to the converter
instability. Certain points must be considered before
starting a layout for the RT8207L/M.
Connect an RC low pass filter from VDDP to VDD; 1μF
and 5.1Ω are recommended. Place the filter capacitor
close to the IC.
Keep current limit setting network as close as possible
to the IC. Routing of the network should avoid coupling
to high voltage switching node.
Connections from the drivers to the respective gate of
the high side or the low side MOSFET should be as
short as possible to reduce stray inductance.
All sensitive analog traces and components such as
VDDQ, FB, PGND, PGOOD, CS, VDD, and TON should
be placed away from high voltage switching nodes such
as PHASE, LGATE, UGATE, and BOOT to avoid
coupling. Use internal layer(s) as ground plane(s) and
shield the feedback trace from power traces and
components.
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
0 25 50 75 100 125
Ambient Temperature (°C)
Maximum Power Dissipation (W) 1
Four-Layer PCB
WQFN-24L 4x4
WQFN-20L 3x3
Thermal Considerations
The junction temperature should never exceed the
absolute maximum junction temperature T
J(MAX)
, listed
under Absolute Maximum Ratings, to avoid permanent
damage to the device. The maximum allowable power
dissipation depends on the thermal resistance of the IC
package, the PCB layout, the rate of surrounding airflow,
and the difference between the junction and ambient
temperatures. The maximum power dissipation can be
calculated using the following formula :
P
D(MAX)
= (T
J(MAX)
T
A
) / θ
JA
where T
J(MAX)
is the maximum junction temperature, T
A
is
the ambient temperature, and θ
JA
is the junction-to-ambient
thermal resistance.
For continuous operation, the maximum operating junction
temperature indicated under Recommended Operating
Conditions is 125°C. The junction-to-ambient thermal
resistance, θ
JA
, is highly package dependent. For a
WQFN-24L 4x4 package, the thermal resistance, θ
JA
, is
52°C/W on a standard JEDEC 51-7 high effective-thermal-
conductivity four-layer test board. For a WQFN-20L 3x3
package, the thermal resistance, θ
JA
, is 68°C/W on a
standard JEDEC 51-7 high effective-thermal-conductivity
four-layer test board. The maximum power dissipation at
T
A
= 25°C can be calculated as below :
P
D(MAX)
= (125°C 25°C) / (52°C/W) = 1.923W for a
WQFN-24L 4x4 package.
P
D(MAX)
= (125°C 25°C) / (68°C/W) = 1.471W for a
WQFN-20L 3x3 package.
The maximum power dissipation depends on the operating
ambient temperature for the fixed T
J(MAX)
and the thermal
resistance, θ
JA
. The derating curves in Figure 9 allows
the designer to see the effect of rising ambient temperature
on the maximum power dissipation.

RT8207LGQW

Mfr. #:
Manufacturer:
Description:
IC REG CTRLR DDR 1OUT 24WQFN
Lifecycle:
New from this manufacturer.
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