3
AT24C32A/64A
3054N–SEEPR–2/04
Pin Description SERIAL CLOCK (SCL): The SCL input is used to positive edge clock data into each
EEPROM device and negative edge clock data out of each device.
SERIAL DATA (SDA): The SDA pin is bidirectional for serial data transfer. This pin is
open-drain driven and may be wire-ORed with any number of other open-drain or open
collector devices.
DEVICE/ADDRESSES (A2, A1, A0): The A2, A1 and A0 pins are device address inputs
that are hardwired or left not connected for hardware compatibility with other AT24Cxx
devices. When the pins are hardwired, as many as eight 32K/64K devices may be
addressed on a single bus system (device addressing is discussed in detail under the
Device Addressing section). If the pins are left floating, the A2, A1 and A0 pins will be
internally pulled down to GND if the capacitive coupling to the circuit board V
CC
plane is
<3 pF. If coupling is >3 pF, Atmel recommends connecting the address pins to GND.
WRITE PROTECT (WP): The write protect input, when connected to GND, allows nor-
mal write operations. When WP is connected high to V
CC
, all write operations to the
memory are inhibited. If the pin is left floating, the WP pin will be internally pulled down
to GND if the capacitive coupling to the circuit board V
CC
plane is <3 pF. If coupling is
>3 pF, Atmel recommends connecting the pin to GND. Switching WP to V
CC
prior to a
write operation creates a software write protect function.
Memory Organization AT24C32A/64A, 32K/64K SERIAL EEPROM: The 32K/64K is internally organized as
128/256 pages of 32 bytes each. Random word addressing requires a 12/13-bit data
word address.
