4
AT24C32A/64A
3054N–SEEPR–2/04
Note: 1. This parameter is characterized and is not 100% tested.
Note: 1. V
IL
min and V
IH
max are reference only and are not tested.
Pin Capacitance
(1)
Applicable over recommended operating range from T
A
= 25° C, f = 1.0 MHz, V
CC
= +1.8V.
Symbol Test Condition Max Units Conditions
C
I/O
Input/Output Capacitance (SDA) 8 pF V
I/O
= 0V
C
IN
Input Capacitance (A
0
, A
1
, A
2
, SCL) 6 pF V
IN
= 0V
DC Characteristics
Applicable over recommended operating range from: T
AI
= -40° C to +85° C, V
CC
= +1.8V to +5.5V, T
AE
= -40° C to +125° C,
V
CC
= +1.8V to +5.5V (unless otherwise noted).
Symbol Parameter Test Condition Min Typ Max Units
V
CC1
Supply Voltage 1.8 5.5 V
V
CC2
Supply Voltage 2.5 5.5 V
V
CC3
Supply Voltage 2.7 5.5 V
V
CC4
Supply Voltage 4.5 5.5 V
I
CC1
Supply Current V
CC
= 5.0V READ at 400 kHz 0.4 1.0 mA
I
CC2
Supply Current V
CC
= 5.0V WRITE at 400 kHz 2.0 3.0 mA
I
SB1
Standby Current
(1.8V option)
V
CC
= 1.8V V
IN
= V
CC
or V
SS
1.0 µA
I
SB2
Standby Current
(2.5V option)
V
CC
= 2.5V V
IN
= V
CC
or V
SS
2.0 µA
I
SB3
Standby Current
(2.7V option)
V
CC
= 2.7V V
IN
= V
CC
or V
SS
2.0 µA
I
SB4
Standby Current
(5V option)
V
CC
= 4.5 - 5.5V V
IN
= V
CC
or V
SS
6.0 µA
I
LI
Input Leakage
Current
V
IN
= V
CC
or
V
SS
0.10 3.0 µA
I
LO
Output Leakage
Current
V
OUT
= V
CC
or
V
SS
0.05 3.0 µA
V
IL
Input Low Level
(1)
-0.6 V
CC
x 0.3 V
V
IH
Input High Level
(1)
V
CC
x 0.7 V
CC
+ 0.5 V
V
OL2
Output Low Level V
CC
= 3.0V I
OL
= 2.1 mA 0.4 V
V
OL1
Output Low Level V
CC
= 1.8V I
OL
= 0.15 mA 0.2 V
5
AT24C32A/64A
3054N–SEEPR–2/04
Notes: 1. This parameter is characterized and is not 100% tested (T
A
= 25° C).
2. This parameter is characterized and is not 100% tested.
3. The Write Cycle Time of 5 ms only applies to the AT24C32A/64A devices bearing the process letter “A” on the package (the
mark is located in the lower right corner on the top side of the package).
AC Characteristics
Applicable over recommended operating range from T
AI
= -40° C to +85° C, T
AE
= -40° C to +125° C, V
CC
= +1.8V to +5.5V,
CL = 1 TTL Gate and
100 pF (unless otherwise noted).
Symbol Parameter
AT24C32A AT24C64A
Units
1.8V 2.5V – 5.0V 1.8V – 3.6V 5.0V
Min Max Min Max Min Max Min Max
f
SCL
Clock Frequency, SCL 100 400 400 400 kHz
t
LOW
Clock Pulse Width Low 4.7 1.3 1.3 1.2 µs
t
HIGH
Clock Pulse Width High 4.0 0.6 0.6 0.6 µs
t
I
Noise Suppression Time
(1)
100 50 100 50 ns
t
AA
Clock Low to Data Out Valid 0.1 4.5 0.1 0.9 0.2 0.9 0.1 0.9 µs
t
BUF
Time the bus must be free
before a new transmission
can start
(2)
4.7 1.3 1.3 1.2 µs
t
HD.STA
Start Hold Time 4.0 0.6 0.6 0.6 µs
t
SU.STA
Start Set-up Time 4.7 0.6 0.6 0.6 µs
t
HD.DAT
Data In Hold Time 0 0 0 0 µs
t
SU.DAT
Data In Set-up Time 200 100 100 100 ns
t
R
Inputs Rise Time
(2)
1.0 0.3 0.3 0.3 µs
t
F
Inputs Fall Time
(2)
300 300 300 300 ns
t
SU.STO
Stop Set-up Time 4.7 0.6 0.6 0.6 µs
t
DH
Data Out Hold Time 100 50 200 50 ns
t
WR
Write Cycle Time 20 or 5
(3)
10 or 5
(3)
20 or 5
(3)
10 or 5
(3)
ms
Endurance
(1)
5.0V, 25° C, Page Mode 1M 1M 1M 1M
Write
Cycles
6
AT24C32A/64A
3054N–SEEPR–2/04
Device Operation CLOCK and DATA TRANSITIONS: The SDA pin is normally pulled high with an exter-
nal device. Data on the SDA pin may change only during SCL low time periods (refer to
Data Validity timing diagram). Data changes during SCL high periods will indicate a start
or stop condition as defined below.
START CONDITION: A high-to-low transition of SDA with SCL high is a start condition
which must precede any other command (refer to Start and Stop Definition timing
diagram).
STOP CONDITION: A low-to-high transition of SDA with SCL high is a stop condition.
After a read sequence, the stop command will place the EEPROM in a standby power
mode (refer to Start and Stop Definition timing diagram).
ACKNOWLEDGE: All addresses and data words are serially transmitted to and from the
EEPROM in 8-bit words. The EEPROM sends a zero during the ninth clock cycle to
acknowledge that it has received each word.
STANDBY MODE: The AT24C32A/64A features a low power standby mode which is
enabled: a) upon power-up and b) after the receipt of the STOP bit and the completion
of any internal operations.
MEMORY RESET: After an interruption in protocol, power loss or system reset, any 2-
wire part can be reset by following these steps:
(a) Clock up to 9 cycles, (b) look for SDA high in each cycle while SCL is high and then
(c) create a start condition as SDA is high.

AT24C32AY1-10YI-2.7

Mfr. #:
Manufacturer:
Description:
IC EEPROM 32K I2C 400KHZ 8MAP
Lifecycle:
New from this manufacturer.
Delivery:
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