70V9289L12PRFI8 Datasheet 70V9289L9PFGI8, 70V9289L7PFG8, 70V9289L7PFG | P1-P3

MARCH 2014

DSC-4856/8

1



Functional Block Diagram

Features:

◆

True Dual-Ported memory cells which allow simultaneous

access of the same memory location

◆

High-speed clock to data access

– Commercial: 7.5/9/12ns (max.)

– Industrial: 9ns (max.)

◆

Low-power operation

– IDT70V9389/289L

Active: 500mW (typ.)

Standby: 1.5mW (typ.)

◆

Flow-Through or Pipelined output mode on either port via

the FT/PIPE pins

◆

Counter enable and reset features

◆

Dual chip enables allow for depth expansion without

additional logic

◆

LVTTL- compatible, single 3.3V (±0.3V) power supply

◆

Full synchronous operation on both ports

– 4ns setup to clock and 0ns hold on all control, data, and

address inputs

– Data input, address, and control registers

– Fast 7.5ns clock to data out in the Pipelined output mode

– Self-timed write allows fast cycle time

– 12ns cycle time, 83MHz operation in Pipelined output

mode

◆

Separate upper-byte and lower-byte controls for

multiplexed bus and bus matching compatibility

◆

Industrial temperature range (–40°C to +85°C) is

available for selected speeds

◆

Available in a 128-pin Thin Quad Flatpack (TQFP) and

100-pin Thin Quad Flatpack (TQFP)

◆

Green parts available, see ordering information

IDT70V9389/289L

0a 1a

0b 1b

0/1

ab

I/O

Control

1

0/1

0

FT

/PIPE

R

R/

W

R

UB

R

LB

R

CE

0R

OE

R

CE

1R

MEMORY

ARRAY

Counter/

Address

Reg.

4856 drw 01

A

15R

A

0R

CLK

R

ADS

R

CNTEN

R

CNTRST

R

I/O

9L

-I/O

17L

(2)

I/O

0L

-I/O

8L

(1)

I/O

9R

-I/O

17R

(1)

I/O

0R

-I/O

8R

(1)

A

15L

Counter/

Address

Reg.

R/

W

L

UB

L

LB

L

CE

0L

OE

L

CE

1L

1

0/1

0

1b 0b

1a 0a

0/1

ba

I/O

Control

FT

/PIPE

L

A

0L

CLK

L

ADS

L

CNTEN

L

CNTRST

L

HIGH-SPEED 3.3V

64K x18/x16

SYNCHRONOUS PIPELINED

DUAL-PORT STATIC RAM

NOTES:

1. I/O

0X - I/O7X for IDT70V9289.

2. I/O

8X - I/O15X for IDT70V9289.

6.42

2

IDT70V9389/289L

High-Speed 3.3V 64K x18/x16 Dual-Port Synchronous Pipelined Static RAM Industrial & Commercial Temperature Ranges

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

102

101

100

99

98

97

96

95

94

93

92

90

89

88

87

86

85

84

83

82

81

80

79

78

77

76

75

74

73

72

70

69

68

67

66

65

91

71

NC

A

9R

A

8R

A

7R

A

6R

A

5R

A

4R

A

3R

A

2R

A

1R

A

0R

NC

CNTEN

R

CLK

R

ADS

R

V

SS

V

DD

NC

A

0L

A

1L

A

2L

A

3L

A

4L

A

5L

A

6L

A

7L

A

8L

A

9L

NC

I/O

12L

I/O

11L

V

DD

NC

I/O

10L

I/O

9L

I/O

8L

V

DD

I/O

7L

I/O

6L

I/O

5L

I/O

4L

V

SS

I/O

3L

I/O

2L

V

SS

I/O

1L

I/O

0L

V

DD

V

SS

I/O

0R

I/O

2R

I/O

1R

V

SS

I/O

4R

I/O

5R

I/O

6R

V

DD

I/O

7R

I/O

8R

I/O

9R

I/O

10R

NC

V

SS

I/O

11R

I/O

12R

V

DD

I/O

3R

70V9389PRF

PK128

(4)

128-Pin TQFP

Top View

(5)

4856 drw 02

A

10R

A

11R

A

12R

A

13R

A

14R

A

15R

NC

LB

R

UB

R

CE

0R

CE

1R

CNTRST

R

V

DD

V

SS

R/W

R

OE

R

FT/PIPE

R

V

SS

I/O

17R

I/O

16R

I/O

15R

I/O

14R

V

DD

V

DD

I/O

13R

A

10L

A

11L

A

12L

A

13L

A

14L

A

15L

NC

LB

L

UB

L

CE

0L

CE

1L

CNTRST

L

V

DD

V

SS

R/W

L

OE

L

FT/PIPE

L

V

SS

I/O

17L

I/O

16L

I/O

15L

I/O

14L

V

DD

V

SS

I/O

13L

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

128

127

126

125

124

123

122

121

120

119

118

117

116

115

114

113

112

111

110

109

108

107

106

105

104

103

CNTEN

L

CLK

L

ADS

L

02/25/14

Description:

The IDT70V9389/289 is a high-speed 64K x 18 (64K x 16) bit

synchronous Dual-Port RAM. The memory array utilizes Dual-Port

memory cells to allow simultaneous access of any address from both ports.

Registers on control, data, and address inputs provide minimal setup and

hold times. The timing latitude provided by this approach allows systems

to be designed with very short cycle times.

Pin Configuration

(1,2,3)

NOTES:

1. All V

DD pins must be connected to power supply.

2. All V

SS pins must be connected to ground.

3. Package body is approximately 14mm x 20mm x 1.4mm.

4. This package code is used to reference the package diagram.

5. This text does not indicate orientation of the actual part-marking.

With an input data register, the IDT70V9389/289 has been

optimized for applications having unidirectional or bidirectional data

flow in bursts. An automatic power down feature, controlled by CE

0

and CE1, permits the on-chip circuitry of each port to enter a very low

standby power mode. Fabricated using CMOS high-performance

technology, these devices typically operate on only 500mW of

power.

6.42

IDT70V9389/289L

High-Speed 3.3V 64K x18/x16 Dual-Port Synchronous Pipelined Static RAM Industrial & Commercial Temperature Ranges

3

INDEX

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76

FT/PIPE

R

OE

R

R/W

R

CNTRST

R

CE

1R

CE

0R

V

SS

A

12R

A

13R

A

11R

A

10R

A

9R

A

14R

I/O

10R

I/O

11R

I/O

12R

I/O

13R

I/O

14R

I/O

15R

V

SS

UB

R

LB

R

4856 drw 02a

I/O

15L

FT/PIPE

L

OE

L

R/W

L

CNTRST

L

CE

1L

CE

0L

V

DD

A

14L

A

13L

A

12L

A

11L

A

10L

A

9L

I/O

10L

I/O

11L

I/O

12L

I/O

13L

I/O

14L

UB

L

LB

L

V

SS

I/O

5R

I/O

4R

I/O

3R

I/O

2R

I/O

0R

I/O

0L

V

SS

I/O

2L

I/O

4L

I/O

5L

I/O

6L

I/O

7L

I/O

3L

I/O

1R

I/O

7R

I/O

8R

I/O

9R

I/O

8L

I/O

9L

I/O

6R

A

7R

A

8L

A

7L

A

6R

A

5R

A

4R

A

3R

A

2R

A

1R

A

0R

CLK

R

CNTEN

R

CLK

L

CNTEN

L

A

0L

A

2L

A

3L

A

5L

A

6L

A

1L

A

4L

A

8R

V

SS

V

DD

I/O1

L

V

DD

V

SS

70V9389PF

PN100

(4)

100-Pin TQFP

Top View

(5)

A

15R

A

15L

I/O

16R

I/O

17R

I/O

17L

I/O

16L

ADS

L

ADS

R

V

SS

,

02/25/14

Pin Configurations

(1,2,3)

(con't.)

NOTES:

1. All V

DD pins must be connected to power supply.

2. All V

SS pins must be connected to ground.

3. Package body is approximately 14mm x 14mm x 1.4mm

4. This package code is used to reference the package diagram.

5. This text does not indicate orientation of the actual part-marking.

70V9289L12PRFI8

70V9289L12PRFI8

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