6.42
14
IDT70V9389/289L
High-Speed 3.3V 64K x18/x16 Dual-Port Synchronous Pipelined Static RAM Industrial & Commercial Temperature Ranges
Timing Waveform of Flow-Through Read-to-Write-to-Read (OE = VIL)
(3)
Timing Waveform of Flow-Through Read-to-Write-to-Read (OE Controlled)
(3)
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2).
2. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals.
3. CE
0, UB, LB, and ADS = VIL; CE1 and CNTRST = VIH. "NOP" is "No Operation".
4. Addresses do not have to be accessed sequentially since ADS = V
IL constantly loads the address on the rising edge of the CLK; numbers are for
reference use only.
5. "NOP" is "No Operation." Data in memory at the selected address may be corrupted and should be re-written to guarantee data integrity.
R/
W
ADDRESS
An
An +1 An + 2 An + 2
An + 3
An + 4
DATA
IN
Dn + 2
CE
0
CLK
4856 drw 12
Qn
DATA
OUT
CE
1
UB, LB
t
CD1
Qn + 1
t
CH1
t
CL1
t
CYC1
t
SD
t
HD
t
CD1
t
CD1
t
DC
t
CKHZ
Qn + 3
t
CD1
t
DC
t
SC
t
HC
t
SB
t
HB
t
SW
t
HW
t
SA
t
HA
READ
NOP
READ
t
CKLZ
(4)
(2)
(1) (1)
t
SW
t
HW
WRITE
(5)
R/
W
ADDRESS
An
An +1 An + 2 An + 3
An + 4
An + 5
(4)
DATA
IN
Dn + 2
CE
0
CLK
4856 drw 13
Qn
DATA
OUT
CE
1
UB, LB
t
CD1
t
CH1
t
CL1
t
CYC1
t
SD
t
HD
t
CD1
t
DC
Qn + 4
t
CD1
t
DC
t
SC
t
HC
t
SB
t
HB
t
SW
t
HW
t
SA
t
HA
READ WRITE READ
t
CKLZ
(2)
Dn + 3
t
OHZ
(1)
(1)
t
SW
t
HW
OE
t
OE
