70V9289L12PRFI8 Datasheet 70V9289L9PFGI8, 70V9289L7PFG8, 70V9289L7PFG | P4-P6

6.42

4

IDT70V9389/289L

High-Speed 3.3V 64K x18/x16 Dual-Port Synchronous Pipelined Static RAM Industrial & Commercial Temperature Ranges

Pin Configurations

(1,2,3)

(con't.)

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

102

101

100

99

98

97

96

95

94

93

92

90

89

88

87

86

85

84

83

82

81

80

79

78

77

76

75

74

73

72

70

69

68

67

66

65

91

71

NC

A

9R

A

8R

A

7R

A

6R

A

5R

A

4R

A

3R

A

2R

A

1R

A

0R

NC

CNTEN

R

CLK

R

ADS

R

V

SS

V

DD

NC

A

0L

A

1L

A

2L

A

3L

A

4L

A

5L

A

6L

A

7L

A

8L

A

9L

NC

I/O

10L

I/O

9L

V

DD

NC

I/O

8L

NC

V

DD

I/O

7L

I/O

6L

I/O

5L

I/O

4L

V

SS

I/O

3L

I/O

2L

V

SS

I/O

1L

I/O

0L

V

DD

V

SS

I/O

0R

I/O

2R

I/O

1R

V

SS

I/O

4R

I/O

5R

I/O

6R

V

DD

I/O

7R

NC

I/O

8R

NC

V

SS

I/O

9R

I/O

10R

I/O

3R

70V9289PRF

PK128

(4)

128-Pin TQFP

Top View

(5)

4856 drw 02b

A

10R

A

11R

A

12R

A

13R

A

14R

A

15R

NC

LB

R

UB

R

CE

0R

CE

1R

CNTRST

R

V

DD

V

SS

R/W

R

OE

R

FT/PIPE

R

V

SS

I/O

15R

I/O

14R

I/O

13R

I/O

12R

V

DD

V

DD

I/O

11R

A

10L

A

11L

A

12L

A

13L

A

14L

A

15L

NC

LB

L

UB

L

CE

0L

CE

1L

CNTRST

L

V

DD

V

SS

R/W

L

OE

L

FT/PIPE

L

V

SS

I/O

15L

I/O

14L

I/O

13L

I/O

12L

V

DD

V

SS

I/O

11L

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

128

127

126

125

124

123

122

121

120

119

118

117

116

115

114

113

112

111

110

109

108

107

106

105

104

103

CNTEN

L

CLK

L

ADS

L

V

DD

02/25/14

NOTES:

1. All V

DD pins must be connected to power supply.

2. All V

SS pins must be connected to ground.

3. Package body is approximately 14mm x 20mm x 1.4mm.

4. This package code is used to reference the package diagram.

5. This text does not indicate orientation of the actual part-marking.

6.42

IDT70V9389/289L

High-Speed 3.3V 64K x18/x16 Dual-Port Synchronous Pipelined Static RAM Industrial & Commercial Temperature Ranges

5

Pin Configurations

(1,2,3)

(con't.)

Index

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76

IDT70V9289PF

PN100

(4)

100-Pin TQFP

Top View

(5)

4856 drw 02c

I/O

15L

OE

L

R/W

L

CNTRST

L

CE

1L

CE

0L

V

DD

NC

A

14L

A

13L

NC

A

12L

A

11L

A

10L

A

9L

I/O

10L

I/O

11L

I/O

12L

I/O

13L

I/O

14L

UB

L

LB

L

V

SS

I/O

6R

I/O

5R

FT/PIPE

R

OE

R

R/W

R

CNTRST

R

CE

1R

CE

0R

NC

V

SS

A

12R

A

13R

A

11R

A

10R

A

9R

A

14R

I/O

10R

I/O

11R

I/O

12R

I/O

13R

I/O

14R

I/O

15R

V

SS

UB

R

LB

R

I/O

4R

I/O

3R

I/O

2R

I/O

0R

I/O

0L

I/O

IL

V

SS

I/O

2L

I/O

4L

I/O

5L

I/O

6L

I/O

7L

I/O

3L

I/O

1R

I/O

7R

NC

I/O

8R

I/O

9R

I/O

8L

I/O

9L

FT/PIPE

L

A

8R

A

7R

A

8L

A

7L

A

6R

A

5R

A

4R

A

3R

A

2R

A

1R

A

0R

CNTEN

R

CLK

R

ADS

R

ADS

L

CLK

L

CNTEN

L

A

0L

V

SS

A

2L

A

3L

A

5L

A

6L

A

1L

A

4L

V

SS

V

DD

V

DD

A

15L

A

15R

.

02/25/14

NOTES:

1. All V

DD pins must be connected to power supply.

2. All V

SS pins must be connected to ground.

3. Package body is approximately 14mm x 14mm x 1.4mm

4. This package code is used to reference the package diagram.

5. This text does not indicate orientation of the actual part-marking.

6.42

6

IDT70V9389/289L

High-Speed 3.3V 64K x18/x16 Dual-Port Synchronous Pipelined Static RAM Industrial & Commercial Temperature Ranges

NOTES:

1. "H" = V

IH, "L" = VIL, "X" = Don't Care.

2. ADS, CNTEN, CNTRST = X.

3. OE is an asynchronous input signal.

4. LB and UB are single buffered regardless of state of FT/PIPE.

5. CEo and CE

1 are single buffered when FT/PIPE = VIL. CEo and CE1 are double buffered when FT/PIPE = VIH, i.e. the signals take two cycles to deselect.

6. I/O

8 - I/O15 for IDT70V9289.

7. I/O

0 - I/O7 for IDT70V9289.

Truth Table I—Read/Write and Enable Control

(1,2,3)

Pin Names

Left Port Right Port Names

CE

0L,

CE

1L

CE

0R,

CE

1R

Chip Enables

(3)

R/W

L

R/W

R

Read/Write Enable

OE

L

OE

R

Output Enable

A

0L

- A

15L

A

0R

- A

15R

Address

I/O

0L

- I/O

17L

(1)

I/O

0R

- I/O

17R

(1)

Data Input/Output

CLK

L

CLK

R

Clock

UB

L

UB

R

Upper Byte Select

(2)

LB

L

LB

R

Lower Byte Select

(2)

ADS

L

ADS

R

Address Strobe Enable

CNTEN

L

CNTEN

R

Counter Enable

CNTRST

L

CNTRST

R

Counter Reset

FT/PIPE

L

FT/PIPE

R

Flow-Through / Pipeline

V

DD

Power (3.3V)

V

SS

Ground (0V)

4856 tbl 01

OE

CLK

CE

0

(5)

CE

1

(5)

UB

(4)

LB

(4)

R/W

Upper Byte

I/O

9-17

(6)

Lower Byte

I/O

0-8

(7)

MODE

X

↑

H X X X X High-Z High-Z Deselected–Power Down

X

↑

X L X X X High-Z High-Z Deselected–Power Down

X

↑

L H H H X High-Z High-Z Both Bytes Deselected

X

↑

LHLHL D

IN

High-Z Write to Upper Byte Only

X

↑

LHHLL High-Z DATA

IN

Write to Lower Byte Only

X

↑

LHLLL DATA

IN

DATA

IN

Write to Both Bytes

L

↑

LHLHH DATA

OUT

High-Z Read Upper Byte Only

L

↑

LHHLH High-Z DATA

OUT

Read Lower Byte Only

L

↑

LHLLH DATA

OUT

DATA

OUT

Read Both Bytes

H X L H L L X High-Z High-Z Outputs Disabled

4856 tbl 02

NOTES:

1. I/O

0X - I/O15X for IDT70V9289.

2. LB and UB are single buffered regardless of state of FT/PIPE.

3. CEo and CE

1 are single buffered when FT/PIPE = VIL,

CEo and CE

1 are double buffered when FT/PIPE = VIH,

i.e. the signals take two cycles to deselect.

70V9289L12PRFI8

70V9289L12PRFI8

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