74LV574_4 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 04 — 14 May 2009 10 of 17
NXP Semiconductors
74LV574
Octal D-type flip-flop; positive edge-trigger; 3-state
Test data is given in Table 9.
Definitions for test circuit:
R
L
= Load resistance.
C
L
= Load capacitance including jig and probe capacitance.
R
T
= Termination resistance should be equal to output impedance Z
o
of the pulse generator.
V
EXT
= External voltage for measuring switching times.
Fig 10. Test circuit for measuring switching times
V
M
V
M
t
W
t
W
10 %
90 %
0 V
V
I
V
I
negative
pulse
positive
pulse
0 V
V
M
V
M
90 %
10 %
t
f
t
r
t
r
t
f
001aae331
V
EXT
V
CC
V
I
V
O
DUT
C
L
R
T
R
L
R
L
G
Table 9. Test data
Supply voltage Input Load V
EXT
V
CC
V
I
t
r
, t
f
C
L
R
L
t
PHL
, t
PLH
t
PZH
, t
PHZ
t
PZL
, t
PLZ
< 2.7 V V
CC
≤ 2.5 ns 50 pF 1 kΩ open GND 2V
CC
2.7 V to 3.6 V 2.7 V ≤ 2.5 ns 15 pF, 50 pF 1 kΩ open GND 2V
CC
≥ 4.5 V V
CC
≤ 2.5 ns 50 pF 1 kΩ open GND 2V
CC
