Integrated Silicon Solution, Inc. — 1-800-379-4774 1
Rev. C
07/29/09
IS61LV256AL
Copyright © 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no
liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on
any published information and before placing orders for products.
FEATURES
• High-speedaccesstimes:
— 10 ns
• Automaticpower-downwhenchipisdeselected
• CMOSlowpoweroperation
— 60 µW(typical)CMOSstandby
— 65 mW (typical) operating
• TTLcompatibleinterfacelevels
• Single3.3Vpowersupply
• Fullystaticoperation:noclockorrefresh
required
• Three-stateoutputs
• Lead-freeavailable
DESCRIPTION
TheISSIIS61LV256ALisaveryhigh-speed,lowpower,
32,768-wordby8-bitstaticRAM.ItisfabricatedusingISSI's
high-performanceCMOStechnology.Thishighlyreliable
process coupled with innovative circuit design techniques,
yieldsaccesstimesasfastas8nsmaximum.
When CEisHIGH(deselected),thedeviceassumesa
standby mode at which the power dissipation is reduced to
150µW(typical)withCMOSinputlevels.
Easymemoryexpansionisprovidedbyusinganactive
LOWChipEnable(CE).TheactiveLOWWriteEnable(WE)
controls both writing and reading of the memory.
The IS61LV256AL is available in the JEDEC standard
28-pin,300-milSOJandthe450-milTSOP(TypeI)pack-
ages.
32K x 8 LOW VOLTAGE
CMOS STATIC RAM
FUNCTIONAL BLOCK DIAGRAM
A0-A14
CE
OE
WE
32KX8
MEMORYARRAY
DECODER
COLUMNI/O
CONTROL
CIRCUIT
GND
VDD
I/O
DATA
CIRCUIT
I/O0-I/O7
AUGUST 2009