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IS61LV256AL-10TLI

P1-P3P4-P6P7-P9P10-P12
Integrated Silicon Solution, Inc. — 1-800-379-4774 7
Rev. C
07/29/09
IS61LV256AL
AC WAVEFORMS
WRITE CYCLE NO. 1
(CE Controlled, OEisHIGHorLOW)
(1 )
DATAUNDEFINED
t
WC
VALIDADDRESS
t
SCE
t
PWE1
t
PWE2
t
AW
t
HA
HIGH-Z
t
HD
t
SA
t
HZWE
ADDRESS
CE
WE
D
OUT
DIN
DATA
IN
VALID
t
LZWE
t
SD
CE_WR1.eps
WRITE CYCLE SWITCHING CHARACTERISTICS
(1,2)
(OverOperatingRange)
-10 ns -12 ns
Symbol Parameter Min. Max. Min. Max. Unit
tw c WriteCycleTime 10 — 12 — ns
ts c e CEtoWriteEnd 8 — 8 — ns
ta w AddressSetupTime 8 — 8 — ns
to Write End
th a AddressHold 0 — 0 — ns
from Write End
ts a AddressSetupTime 0 — 0 — ns
tP w e 1 WEPulseWidth(OEHIGH) 7 — 8 — ns
tP w e 2 WEPulseWidth(OELOW) 10 — 12 — ns
ts d DataSetuptoWriteEnd 6.5 — 7 — ns
th d DataHoldfromWriteEnd 0 — 0 — ns
th z w e
(3)
WELOWtoHigh-ZOutput — 3.5 — 5 ns
tl z w e
(3)
WEHIGHtoLow-ZOutput 0 — 0 — ns
Notes:
1. Testconditionsassumesignaltransitiontimesof3nsorless,timingreferencelevelsof1.5V,inputpulselevelsof0to3.0V
andoutputloadingspeciedinFigure1.
2. TheinternalwritetimeisdenedbytheoverlapofCELOWandWELOW.Allsignalsmustbeinvalidstatestoinitiatea
Write,butanyonecangoinactivetoterminatetheWrite.TheDataInputSetupandHoldtimingarereferencedtotherisingor
falling edge of the signal that terminates the Write.
3. TestedwiththeloadinFigure2.Transitionismeasured±500mVfromsteady-statevoltage.Not100%tested.
IS61LV256AL
8 Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. C
07/29/09
DATAUNDEFINED
LOW
t
WC
VALIDADDRESS
t
PWE1
t
AW
t
HA
HIGH-Z
t
HD
t
SA
t
HZWE
ADDRESS
CE
WE
D
OUT
D
IN
OE
DATA
IN
VALID
t
LZWE
t
SD
CE_WR2.eps
WRITE CYCLE NO. 2
(WE Controlled, OEisHIGHDuringWriteCycle)
(1,2)
WRITE CYCLE NO. 3
(WE Controlled, OE isLOWDuringWriteCycle)
(1)
DATAUNDEFINED
t
WC
VALIDADDRESS
LOW
LOW
t
PWE2
t
AW
t
HA
HIGH-Z
t
HD
t
SA
t
HZWE
ADDRESS
CE
WE
D
OUT
D
IN
OE
DATA
IN
VALID
t
LZWE
t
SD
CE_WR3.eps
Notes:
1. TheinternalwritetimeisdenedbytheoverlapofCELOWandWELOW.AllsignalsmustbeinvalidstatestoinitiateaWrite,
butanyonecangoinactivetoterminatetheWrite.TheDataInputSetupandHoldtimingarereferencedtotherisingorfalling
edge of the signal that terminates the Write.
2. I/OwillassumetheHigh-ZstateifOE > V
I h .
Integrated Silicon Solution, Inc. — 1-800-379-4774 9
Rev. C
07/29/09
IS61LV256AL
DATA RETENTION SWITCHING CHARACTERISTICS
Symbol Parameter Test Condition Min. Typ.
(1)
Max. Unit
Vd r Vd d forDataRetention SeeDataRetentionWaveform 2.0 3.6 V
Id r DataRetentionCurrent Vd d =2.0V,CE ≥Vd d –0.2V Com. — 2 40 µA
VI n ≥ Vd d – 0.2V, or VI n
≤
Vs s + 0.2V
Ind. — — 50
ts d r DataRetentionSetupTime SeeDataRetentionWaveform 0 — ns
tr d r RecoveryTime SeeDataRetentionWaveform tr c — ns
Note:
1.TypicalValuesaremeasuredatVd d =3.3V,Ta = 25
o
Candnot100%tested.
DATA RETENTION WAVEFORM (CE Controlled)
VDD
CE ≥ VDD
- 0.2V
t
SDR
t
RDR
V
DR
CE
GND
Data Retention Mode
P1-P3P4-P6P7-P9P10-P12

IS61LV256AL-10TLI

Mfr. #:
Buy IS61LV256AL-10TLI
Manufacturer:
ISSI
Description:
SRAM 256K 32Kx8 10ns Async SRAM 3.3v
Lifecycle:
New from this manufacturer.
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