LTC6820
19
6820fb
For more information www.linear.com/LTC6820
APPLICATIONS INFORMATION
isoSPI Setup
The LTC6820 allows each application to be optimized for
power consumption or for noise immunity. The power
and noise immunity of an isoSPI system is determined
by the programmed I
B
current. The I
B
current can range
from 0.1mA to 1mA. A low I
B
reduces the isoSPI power
consumption in the READY and ACTIVE states, while a
high I
B
increases the amplitude of the differential signal
voltage V
A
across the matching termination resistor, R
M
.
I
B
is programmed by the sum of the R
B1
and R
B2
resis-
tors connected between the I
BIAS
pin and GND. For most
applications setting I
B
to 0.5mA is a good compromise
between power consumption and noise immunity. Using
this I
B
setting with a 1:1 transformer and R
M
= 120Ω, R
B1
should be set to 2.8k and R
B2
set to 1.2k. In a typical CAT5
twisted pair these settings will allow for communication
up to 50m.
For applications that require cables longer than 50m it is
recommended to increase the amplitude V
A
by increasing
I
B
to 1mA. This compensates for the increased insertion
loss in the cable and maintains high noise immunity. So
when using cables over 50m and, again, using a trans
-
former with a 1:1 turns ratio and R
M
= 120Ω, R
B1
would
be 1.4k and R
B2
would be 600Ω.
Other I
B
settings can be used to reduce power consumption
or increase the noise immunity as required by the applica-
tion. In these cases when setting V
ICMP
and choosing R
B1
and R
B2
resistor values the following rules should be used:
For cables 50 meters or less:
I
B
= 0.5mA
V
A
= (20 • I
B
) • (R
M
/2)
V
TCMP
= 1/2 • V
A
V
ICMP
= 2 • V
TCMP
R
B2
= V
ICMP
/I
B
R
B1
=
2V
I
B
– R
B2
For cables over 50 meters:
I
B
= 1mA
V
A
= (20 • I
B
) • (R
M
/2)
V
TCMP
= 1/4 • V
A
V
ICMP
= 2 • V
TCMP
R
B2
= V
ICMP
/I
B
R
B1
=
2V
I
B
– R
B2
The maximum data rate of an isoSPI link is determined by
the length of the cable used. For cables 10 meters or less
the maximum 1MHz SPI clock frequency is possible. As
the length of the cable increases the maximum possible
SPI clock rate decreases. This is a result of the increased
propagation delays through the cable creating possible
timing violations.
Cable delay affects three timing specifications, t
CLK
, t
6
, and
t
7
. In the Electrical Characteristics table, each is derated by
100ns to allow for 50ns of cable delay. For longer cables,
the minimum timing parameters may be calculated as
shown below:
t
CLK
, t
6
, and t
7
> 0.9µs + 2 • t
CABLE
Pull-Up Resistance Considerations
The data output (MOSI if MSTR = 0, MISO if MSTR =
1) requires a pull-up resistor, R
PU
. The rise time t
RISE
is
determined by R
PU
and the capacitance on the pin. R
PU
must be small enough to provide adequate setup and hold
times. For a slave device, the time constant must be less
than t
12
and t
14
. In fast mode, 50ns is recommended.
R
PU
< 50ns/C
LOAD
Larger pull-up resistances, up to 5k, can be used in slow
mode.
