LTC6820
4
6820fb
For more information www.linear.com/LTC6820
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full specified
junction temperature range, otherwise specifications are at T
A
= 25°C. V
DD
= 2.7V to 5.5V, V
DDS
= 1.7V to 5.5V, R
BIAS
= 2k to 20k
unless otherwise specified. All voltages are with respect to GND.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
I
LEAK(DIG)
Digital Pin Input Leakage Current PHA, POL, MSTR, SLOW = 0V to V
DD
CS, SCK, MOSI, MISO, EN = 0V to V
DDS
l
±1 µA
C
I/O
Input/Output Pin Capacitance (Note 9) 10 pF
Isolated Pulse Timing (See Figure 2)
t
1/2PW(CS)
Chip-Select Half-Pulse Width
l
120 150 180 ns
t
INV(CS)
Chip-Select Pulse Inversion Delay
l
200 ns
t
DEL(CS)
Chip-Select Response Delay
l
140 190 ns
t
½PW(D)
Data Half-Pulse Width
l
40 50 60 ns
t
INV(D)
Data Pulse Inversion Delay
l
70 ns
t
DEL(D)
Data Response Delay (Note 8)
l
75 120 ns
isoSPI™ Timing—Master (See Figures 3, 4)
t
CLK
SCK Latching Edge to SCK Latching Edge (Note 7) SLOW = 0
SLOW = 1
l
l
1
5
µs
µs
t
1
MOSI Setup Time Before SCK Latching Edge (Note 8)
l
25 ns
t
2
MOSI Hold Time After SCK Latching Edge
l
25 ns
t
3
SCK Low t
CLK
= t
3
+ t
4
≥ 1µs
l
50 ns
t
4
SCK High t
CLK
= t
3
+ t
4
≥ 1µs
l
50 ns
t
5
CS Rising Edge to CS Falling Edge
l
0.6 µs
t
6
SCK Latching Edge to CS Rising Edge (Note 7)
l
1 µs
t
7
CS Falling Edge to SCK Latch Edge (Note 7)
l
1 µs
t
8
SCK Non-Latch Edge to MISO Valid (Note 8)
l
55 ns
t
9
SCK Latching Edge to Short ±1 Transmit
l
50 ns
t
10
CS Transition to Long ±1 Transmit
l
55 ns
t
11
CS Rising Edge to MISO Rising (Note 8)
l
55 ns
isoSPI Timing—Slave (See Figures 3, 4)
t
12
isoSPI Data Recognized to SCK
Latching Edge
(Note 8)
SLOW = 0
SLOW = 1
l
l
110
0.9
145
1.1
185
1.4
ns
µs
t
13
SCK Pulse Width SLOW = 0
SLOW = 1
l
l
90
0.9
115
1.1
150
1.4
ns
µs
t
14
SCK Non-Latch Edge to isoSPI Data Transmit (Note 8) SLOW = 0
SLOW = 1
l
l
115
0.9
145
1.1
190
1.4
ns
µs
t
15
CS Falling Edge to SCK Non-Latch Edge PHA = 1 SLOW = 0
SLOW = 1
l
l
90
0.9
120
1.1
160
1.4
ns
µs
t
16
CS Falling Edge to isoSPI Data Transmit SLOW = 0
SLOW = 1
l
l
200
1.8
265
2.2
345
2.8
ns
µs
t
17
CS Rising Edge to SCK Latching Edge PHA = 1 SLOW = 0
SLOW = 1
l
l
90
0.9
120
1.1
160
1.4
ns
µs
t
18
CS Rising Edge to MOSI Rising Edge (Note 8)
l
35 ns
t
RTN
Data Return Delay SLOW = 0
SLOW = 1
l
l
485
3.3
625
4
ns
µs
Note 1:
Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All currents into pins are positive, and all voltages are referenced
to GND unless otherwise specified.
Note 3: The LTC6820I is guaranteed to meet specified performance
from –40°C to 85°C. The LTC6820H is guaranteed to meet specified
performance from –40°C to 125°C.
Note 4: Active supply current (I
DD
) is dependent on the amount of time
that the output drivers are active on IP and IM. During those times I
DD
will
increase by the 20 • I
B
drive current. For the maximum data rate 1MHz,
the drivers are active approximately 10% of the time if MSTR = 1, and 5%
