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OM11014

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P54P55-P57P58-P60P61-P63P64-P66P67-P67
LPC2917_19_1 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 01 — 31 July 2008 10 of 67
NXP Semiconductors
LPC2917/19
ARM9 microcontroller with CAN and LIN
7. Functional description
7.1 Reset, debug, test and power description
7.1.1 Reset and power-up behavior
The LPC2917/19 contains external reset input and internal power-up reset circuits. This
ensures that a reset is extended internally until the oscillators and flash have reached a
stable state. See Section 11 for trip levels of the internal power-up reset circuit
1
. See
Section 12 for characteristics of the several start-up and initialization times. Table 4 shows
the reset pin.
At activation of the RST_N pin the JTAGSEL pin is sensed as logic LOW. If this is the case
the LPC2917/19 is assumed to be connected to debug hardware, and internal circuits
reprogram the source for the BASE_SYS_CLK to be the crystal oscillator instead of the
Low-Power Ring Oscillator (LP_OSC). This is required because the clock rate when
running at LP_OSC speed is too low for the external debugging environment.
7.1.2 Reset strategy
The LPC2917/19 contains a central module, the Reset Generation Unit (RGU) in the
Power, Clock and Reset SubSystem (PCRSS), which controls all internal reset signals
towards the peripheral modules. The RGU provides individual reset control as well as the
monitoring functions needed for tracing a reset back to source.
P2[17]/RXD1/PCAP1[0]/BLS3 130 GPIO 2, pin 17 UART1 RXD PWM1 CAP0 EXTBUS BLS3
V
DD(IO)
131 3.3 V power supply for I/O
P0[18]/IN2[2]/PMAT2[0]/A14 132 GPIO 0, pin 18 ADC2 IN2 PWM2 MAT0 EXTBUS A14
P0[19]/IN2[3]/PMAT2[1]/A15 133 GPIO 0, pin 19 ADC2 IN3 PWM2 MAT1 EXTBUS A15
P3[4]/MAT3[2]/PMAT2[4]/TXDC1 134 GPIO 3, pin 4 TIMER3 MAT2 PWM2 MAT4 CAN1 TXDC
P3[5]/MAT3[3]/PMAT2[5]/RXDC1 135 GPIO 3, pin 5 TIMER3 MAT3 PWM2 MAT5 CAN1 RXDC
P2[18]/PCAP1[1]/D16 136 GPIO 2, pin 18 - PWM1 CAP1 EXTBUS D16
P2[19]/PCAP1[2]/D17 137 GPIO 2, pin 19 - PWM1 CAP2 EXTBUS D17
P0[20]/IN2[4]/PMAT2[2]/A16 138 GPIO 0, pin 20 ADC2 IN4 PWM2 MAT2 EXTBUS A16
P0[21]/IN2[5]/PMAT2[3]/A17 139 GPIO 0, pin 21 ADC2 IN5 PWM2 MAT3 EXTBUS A17
P0[22]/IN2[6]/PMAT2[4]/A18 140 GPIO 0, pin 22 ADC2 IN6 PWM2 MAT4 EXTBUS A18
V
SS(IO)
141 ground for I/O
P0[23]/IN2[7]/PMAT2[5]/A19 142 GPIO 0, pin 23 ADC2 IN7 PWM2 MAT5 EXTBUS A19
P2[20]/PCAP2[0]/D18 143 GPIO 2, pin 20 - PWM2 CAP0 EXTBUS D18
TDI 144 IEEE 1149.1 data in, pulled up internally
Table 3. LQFP144 pin assignment
…continued
Pin name Pin Description
Default function Function 1 Function 2 Function 3
1. Only for 1.8 V power sources
Table 4. Reset pin
Symbol Direction Description
RST_N IN external reset input, active LOW; pulled up internally
LPC2917_19_1 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 01 — 31 July 2008 11 of 67
NXP Semiconductors
LPC2917/19
ARM9 microcontroller with CAN and LIN
7.1.3 IEEE 1149.1 interface pins (JTAG boundary-scan test)
The LPC2917/19 contains boundary-scan test logic according to IEEE 1149.1, also
referred to in this document as JTAG. The boundary-scan test pins can be used to
connect a debugger probe for the embedded ARM processor. Pin JTAGSEL selects
between boundary-scan mode and debug mode. Table 5 shows the boundary- scan test
pins.
7.1.4 Power supply pins description
Table 6 shows the power supply pins.
7.2 Clocking strategy
7.2.1 Clock architecture
The LPC2917/19 contains several different internal clock areas. Peripherals like Timers,
SPI, UART, CAN and LIN have their own individual clock sources called Base Clocks. All
base clocks are generated by the Clock Generation Unit (CGU). They may be unrelated in
frequency and phase and can have different clock sources within the CGU.
The system clock for the CPU and AHB Bus infrastructure has its own base clock. This
means most peripherals are clocked independently from the system clock. See Figure 3
for an overview of the clock areas within the device.
Within each clock area there may be multiple branch clocks, which offers very flexible
control for power-management purposes. All branch clocks are outputs of the Power
Management Unit (PMU) and can be controlled independently. Branch clocks derived
from the same base clock are synchronous in frequency and phase. See Section 8.8 for
more details of clock and power control within the device.
Table 5. IEEE 1149.1 boundary-scan test and debug interface
Symbol Description
JTAGSEL TAP controller select input. LOW-level selects ARM debug mode and HIGH-level
selects boundary scan and flash programming; pulled up internally
TRST_N test reset input; pulled up internally (active LOW)
TMS test mode select input; pulled up internally
TDI test data input, pulled up internally
TDO test data output
TCK test clock input
Table 6. Power supplies
Symbol Description
V
DD(CORE)
digital core supply 1.8 V
V
SS(CORE)
digital core ground (digital core, ADC1/2)
V
DD(IO)
I/O pins supply 3.3 V
V
SS(IO)
I/O pins ground
V
DD(OSC)
oscillator and PLL supply
V
SS(OSC)
oscillator ground
V
DDA(ADC3V3)
ADC1/2 3.3 V supply
V
SS(PLL)
PLL ground
LPC2917_19_1 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 01 — 31 July 2008 12 of 67
NXP Semiconductors
LPC2917/19
ARM9 microcontroller with CAN and LIN
7.2.2 Base clock and branch clock relationship
The next table contains an overview of all the base blocks in the LPC2917/19 and their
derived branch clocks. A short description is given of the hardware parts that are clocked
with the individual branch clocks. In relevant cases more detailed information can be
Fig 3. LPC2917/19 block diagram, overview of clock areas
002aad839
ARM968E-S
DTCM
16 kB
ITCM
16 kB
TEST/DEBUG
INTERFACE
MEMORY
SUBSYSTEM
SYSTEM CONTROL
TIMER0/1 MTMR
CAN0/1
GLOBAL
ACCEPTANCE
FILTER
LIN0/1
PWM0/1/2/3
ADC1/2
EVENT ROUTER
GENERAL PURPOSE I/O
TIMER 0/1/2/3
SPI0/1/2
UART0/1
WDT
AHB TO APB
BRIDGE
AHB TO DTL
BRIDGE
VECTORED
INTERRUPT
CONTROLLER
AHB TO DTL
BRIDGE
AHB TO APB
BRIDGE
AHB TO APB
BRIDGE
AHB TO APB
BRIDGE
RESET/CLOCK
GENERATION
POWER
MANAGEMENT
LPC2917/2919
JTAG
interface
TMR_CLK
SPI_CLK
UART_CLK
SAFE_CLK
IVNSS_CLK
PCR_CLK
SYS_CLK
MSCSS_CLK
ADC_CLK
AHB bus
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P54P55-P57P58-P60P61-P63P64-P66P67-P67

OM11014

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NXP Semiconductors
Description:
LPC2919 EVAL BRD
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