OM11014 Datasheet LPC2919FBD144/01/,, LPC2917FBD144/01/,, OM11014 | P13-P15

Product data sheet Rev. 01 — 31 July 2008 13 of 67

NXP Semiconductors

LPC2917/19

ARM9 microcontroller with CAN and LIN

found in the speciﬁc subsystem description. Some branch clocks have special protection

since they clock vital system parts of the device and should (for example) not be switched

off. See Section 8.8.6 for more details of how to control the individual branch clocks.

Table 7. Base clock and branch clock overview

Base clock Branch clock name Parts of the device clocked by

this branch clock

Remark

BASE_SAFE_CLK CLK_SAFE watchdog timer

[1]

BASE_SYS_CLK CLK_SYS_CPU ARM968E-S and TCMs

CLK_SYS_SYS AHB bus infrastructure

CLK_SYS_PCRSS AHB side of bridge in PCRSS

CLK_SYS_FMC Flash Memory Controller

CLK_SYS_RAM0 Embedded SRAM Controller 0

(32 kB)

CLK_SYS_RAM1 Embedded SRAM Controller 1

(16 kB)

CLK_SYS_SMC External Static Memory

Controller

CLK_SYS_GESS General Subsystem

CLK_SYS_VIC Vectored Interrupt Controller

CLK_SYS_PESS Peripheral Subsystem

[2] [4]

CLK_SYS_GPIO0 GPIO bank 0

CLK_SYS_GPIO1 GPIO bank 1

CLK_SYS_GPIO2 GPIO bank 2

CLK_SYS_GPIO3 GPIO bank 3

CLK_SYS_IVNSS_A AHB side of bridge of IVNSS

BASE_PCR_CLK CLK_PCR_SLOW PCRSS, CGU, RGU and PMU

logic clock

[1]

[3]

BASE_IVNSS_CLK CLK_IVNSS_APB APB side of the IVNSS

CLK_IVNSS_CANCA CAN controller Acceptance Filter

CLK_IVNSS_CANC0 CAN channel 0

CLK_IVNSS_CANC1 CAN channel 1

CLK_IVNSS_LIN0 LIN channel 0

CLK_IVNSS_LIN1 LIN channel 1

BASE_MSCSS_CLK CLK_MSCSS_APB APB side of the MSCSS

CLK_MSCSS_MTMR0 Timer 0 in the MSCSS

CLK_MSCSS_MTMR1 Timer 1 in the MSCSS

CLK_MSCSS_PWM0 PWM 0

CLK_MSCSS_PWM1 PWM 0

CLK_MSCSS_PWM2 PWM 0

CLK_MSCSS_PWM3 PWM 0

CLK_MSCSS_ADC1_A

APB side of ADC 1

CLK_MSCSS_ADC2_A

APB side of ADC 2

Product data sheet Rev. 01 — 31 July 2008 14 of 67

NXP Semiconductors

LPC2917/19

ARM9 microcontroller with CAN and LIN

[1] This clock is always on (cannot be switched off for system safety reasons)

[2] In the peripheral subsystem parts of the Timers, watchdog timer, SPI and UART have their own clock

source. See Section 8.4 for details.

[3] In the Power Clock and Reset Control subsystem parts of the CGU, RGU PMU have their own clock source.

See Section 8.8 for details.

[4] The clock should remain activated when system wake-up on timer or UART is required.

8. Block description

8.1 Flash memory controller

8.1.1 Overview

The Flash Memory Controller (FMC) interfaces to the embedded ﬂash memory for two

tasks:

• Providing memory data transfer

• Memory conﬁguration via triggering, programming and erasing

The ﬂash memory has a 128-bit wide data interface and the ﬂash controller offers two

128-bit buffer lines to improve system performance. The ﬂash has to be programmed

initially via JTAG. In-system programming must be supported by the bootloader.

In-application programming is possible. Flash memory contents can be protected by

disabling JTAG access. Suspension of burning or erasing is not supported.

The key features are:

• Programming by CPU via AHB

• Programming by external programmer via JTAG

• JTAG access protection

• Burn-ﬁnished and erase-ﬁnished interrupt

BASE_UART_CLK CLK_UART0 UART 0 interface clock

CLK_UART1 UART 1 interface clock

BASE_SPI_CLK CLK_SPI0 SPI 0 interface clock

CLK_SPI1 SPI 1 interface clock

CLK_SPI2 SPI 2 interface clock

BASE_TMR_CLK CLK_TMR0 Timer 0 clock for counter part

CLK_TMR1 Timer 1 clock for counter part

CLK_TMR2 Timer 2 clock for counter part

CLK_TMR3 Timer 3 clock for counter part

BASE_ADC_CLK CLK_ADC1 Control of ADC 1, capture sample

result

CLK_ADC2 Control of ADC 2, capture sample

result

BASE_CLK_TESTSHELL CLK_TESTSHELL_IP

Table 7. Base clock and branch clock overview

…continued

Base clock Branch clock name Parts of the device clocked by

this branch clock

Remark

Product data sheet Rev. 01 — 31 July 2008 15 of 67

NXP Semiconductors

LPC2917/19

ARM9 microcontroller with CAN and LIN

8.1.2 Description

After reset ﬂash initialization is started, which takes t

init

time, see Section 12. During this

initialization ﬂash access is not possible and AHB transfers to ﬂash are stalled, blocking

the AHB bus.

During ﬂash initialization the index sector is read to identify the status of the JTAG access

protection and sector security. If JTAG access protection is active the ﬂash is not

accessible via JTAG. ARM debug facilities are disabled to protect the ﬂash memory

contents against unwanted reading out externally. If sector security is active only the

concerned sections are read.

Flash can be read synchronously or asynchronously to the system clock. In synchronous

operation the ﬂash goes into standby after returning the read data. Started reads cannot

be stopped, and speculative reading and dual buffering are therefore not supported.

With asynchronous reading, transfer of the address to the ﬂash and of read data from the

ﬂash is done asynchronously, giving the fastest possible response time. Started reads can

be stopped, so speculative reading and dual buffering are supported.

Buffering is offered because the ﬂash has a 128-bit wide data interface while the AHB

interface has only 32 bits. With buffering a buffer line holds the complete 128-bit ﬂash

word, from which four words can be read. Without buffering every AHB data port read

starts a ﬂash read. A ﬂash read is a slow process compared to the minimum AHB cycle

time, so with buffering the average read time is reduced. This can improve system

performance.

With single buffering the most recently read ﬂash word remains available until the next

ﬂash read. When an AHB data-port read transfer requires data from the same ﬂash word

as the previous read transfer, no new ﬂash read is done and the read data is given without

wait cycles.

When an AHB data-port read transfer requires data from a different ﬂash word to that

involved in the previous read transfer, a new ﬂash read is done and wait states are given

until the new read data is available.

With dual buffering a secondary buffer line is used, the output of the ﬂash being

considered as the primary buffer. On a primary buffer hit data can be copied to the

secondary buffer line, which allows the ﬂash to start a speculative read of the next ﬂash

word.

Both buffer lines are invalidated after:

• Initialization

• Conﬁguration-register access

• Data-latch reading

• Index-sector reading

The modes of operation are listed in Table 8.

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27 P28-P30 P31-P33 P34-P36 P37-P39 P40-P42 P43-P45 P46-P48 P49-P51 P52-P54 P55-P57 P58-P60 P61-P63 P64-P66 P67-P67

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