LPC2917_19_1 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 01 — 31 July 2008 22 of 67
NXP Semiconductors
LPC2917/19
ARM9 microcontroller with CAN and LIN
Latched events remain active until they are explicitly cleared
Programmable input level and edge polarity
Event detection maskable
Event detection is fully asynchronous, so no clock is required
8.3.4.2 Description
The event router allows the event source to be defined, its polarity and activation type to
be selected and the interrupt to be masked or enabled. The event router can be used to
start a clock on an external event.
The vectored interrupt-controller inputs are active HIGH.
8.3.4.3 Event-router pin description and mapping to register bit positions
The event router module in the LPC2917/19 is connected to the pins listed below. The
pins are combined with other functions on the port pins of the LPC2917/19. Table 13
shows the pins connected to the event router, and also the corresponding bit position in
the event-router registers and the default polarity.
8.4 Peripheral subsystem
8.4.1 Peripheral subsystem clock description
The peripheral subsystem is clocked by a number of different clocks:
CLK_SYS_PESS
Table 13. Event-router pin connections
Symbol Direction Bit position Description Default
polarity
EXTINT0 IN 0 external interrupt input 0 1
EXTINT1 IN 1 external interrupt input 1 1
EXTINT2 IN 2 external interrupt input 2 1
EXTINT3 IN 3 external interrupt input 3 1
EXTINT4 IN 4 external interrupt input 4 1
EXTINT5 IN 5 external interrupt input 5 1
EXTINT6 IN 6 external interrupt input 6 1
EXTINT7 IN 7 external interrupt input 7 1
CAN0 RXDC IN 8 CAN0 receive data input wake-up 0
CAN1 RXDC IN 9 CAN1 receive data input wake-up 0
- - 13 to 10 reserved -
LIN0 RXDL IN 14 LIN0 receive data input wake-up 0
LIN1 RXDL IN 15 LIN1 receive data input wake-up 0
- - 21 to 16 reserved -
- na 22 CAN interrupt (internal) 1
- na 23 VIC FIQ (internal) 1
- na 24 VIC IRQ (internal) 1
- - 26 to 25 reserved -
LPC2917_19_1 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 01 — 31 July 2008 23 of 67
NXP Semiconductors
LPC2917/19
ARM9 microcontroller with CAN and LIN
CLK_UART0/1
CLK_SPI0/1/2
CLK_TMR0/1/2/3
CLK_SAFE see Section 7.2.2
8.4.2 Watchdog timer
8.4.2.1 Overview
The purpose of the watchdog timer is to reset the ARM9 processor within a reasonable
amount of time if the processor enters an error state. The watchdog generates a system
reset if the user program fails to trigger it correctly within a predetermined amount of time.
Key features:
Internal chip reset if not periodically triggered
Timer counter register runs on always-on safe clock
Optional interrupt generation on watchdog time-out
Debug mode with disabling of reset
Watchdog control register change-protected with key
Programmable 32-bit watchdog timer period with programmable 32-bit prescaler.
8.4.2.2 Description
The watchdog timer consists of a 32-bit counter with a 32-bit prescaler.
The watchdog should be programmed with a time-out value and then periodically
restarted. When the watchdog times out it generates a reset through the RGU.
To generate watchdog interrupts in watchdog debug mode the interrupt has to be enabled
via the interrupt enable register. A watchdog-overflow interrupt can be cleared by writing
to the clear-interrupt register.
Another way to prevent resets during debug mode is via the Pause feature of the
watchdog timer. The watchdog is stalled when the ARM9 is in debug mode and the
PAUSE_ENABLE bit in the watchdog timer control register is set.
The Watchdog Reset output is fed to the Reset Generation Unit (RGU). The RGU
contains a reset source register to identify the reset source when the device has gone
through a reset. See Section 8.8.5.
8.4.2.3 Pin description
The watchdog has no external pins.
8.4.2.4 Watchdog timer clock description
The watchdog timer is clocked by two different clocks; CLK_SYS_PESS and CLK_SAFE,
see Section 7.2.2. The register interface towards the system bus is clocked by
CLK_SYS_PESS. The timer and prescale counters are clocked by CLK_SAFE which is
always on.
LPC2917_19_1 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 01 — 31 July 2008 24 of 67
NXP Semiconductors
LPC2917/19
ARM9 microcontroller with CAN and LIN
8.4.3 Timer
8.4.3.1 Overview
The LPC2917/19 contains six identical timers: four in the peripheral subsystem and two in
the Modulation and Sampling Control SubSystem (MSCSS) located at different peripheral
base addresses. This section describes the four timers in the peripheral subsystem. Each
timer has four capture inputs and/or match outputs. Connection to device pins depends on
the configuration programmed into the port function-select registers. The two timers
located in the MSCSS have no external capture or match pins, but the memory map is
identical, see Section 8.7.7. One of these timers has an external input for a pause
function.
The key features are:
32-bit timer/counter with programmable 32-bit prescaler
Up to four 32-bit capture channels per timer. These take a snapshot of the timer value
when an external signal connected to the TIMERx CAPn input changes state. A
capture event may also optionally generate an interrupt
Four 32-bit match registers per timer that allow:
Continuous operation with optional interrupt generation on match
Stop timer on match with optional interrupt generation
Reset timer on match with optional interrupt generation
Up to four external outputs per timer corresponding to match registers, with the
following capabilities:
Set LOW on match
Set HIGH on match
Toggle on match
Do nothing on match
Pause input pin (MSCSS timers only)
8.4.3.2 Description
The timers are designed to count cycles of the clock and optionally generate interrupts or
perform other actions at specified timer values, based on four match registers. They also
include capture inputs to trap the timer value when an input signal changes state,
optionally generating an interrupt. The core function of the timers consists of a 32 bit
‘prescale counter’ triggering the 32 bit ‘timer counter’. Both counters run on clock
CLK_TMRx (x runs from 0 to 3) and all time references are related to the period of this
clock. Note that each timer has its individual clock source within the Peripheral
SubSystem. In the Modulation and Sampling SubSystem each timer also has its own
individual clock source. See section Section 8.8.6 for information on generation of these
clocks.
8.4.3.3 Pin description
The four timers in the peripheral subsystem of the LPC2917/19 have the pins described
below. The two timers in the modulation and sampling subsystem have no external pins
except for the pause pin on MSCSS timer 1. See Section 8.7.7 for a description of these

OM11014

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NXP Semiconductors
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LPC2919 EVAL BRD
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