MCF5281CVM80 Datasheet MCF5281CVM80, MCF5281CVM66, MCF5282CVM66 | P1-P3

This document identifies implementation differences between the MCF5281/82 processors and the description

contained in the MCF5282 ColdFire

Reference Manual. Refer to http://www.freescale.com/coldfire for the latest

updates.

All current MCF5281/82 devices are marked as L95M mask set. The date code on the marking can be used to

determine which errata have been corrected on a particular device as shown in Table 1. The datecode format is

XXXYYWW, where YY represents the year and WW represents the work week. The three leading digits can be

ignored.

Table 1. Summary of MCF5281/82 Errata

Errata Module Affected Date Errata

Added

Date Code Affected?

<XXX0324 XXX0324 to

XXX0326

>XXX0326

SECF035 PLL 3/18/03 Yes No No

SECF003 BDM 3/28/03 Yes Yes Yes

SECF002 EMAC 3/28/03 Yes Yes No

SECF021 Cache 3/31/03 Yes Yes No

SECF004 Flash 4/09/03 Yes Yes No

SECF005 Cache 7/21/03 Yes Yes Yes

SECF001 Cache 7/21/03 Yes Yes Yes

SECF029 FlexCAN 7/23/03 Yes Yes Yes

SECF009 FEC 4/22/04 Yes Yes Yes

SECF007 FEC 4/22/04 Yes Yes Yes

SECF036 PLL 8/23/04 Yes Yes Yes

SECF010 FEC 9/14/04 Yes Yes Yes

Table continues on the next page...

Freescale Semiconductor

MCF5282DE

Chip Errata

Rev 8, 02/2015

MCF5282 Chip Errata

Silicon Revision: All

Table 1. Summary of MCF5281/82 Errata (continued)

Errata Module Affected Date Errata

Added

Date Code Affected?

<XXX0324 XXX0324 to

XXX0326

>XXX0326

SECF038 QADC 3/15/05 Yes Yes Yes

SECF031 GPIO 1/6/06 Yes Yes Yes

SECF037 PLL 6/12/06 Yes Yes Yes

SECF006 FEC 5/31/07 Yes Yes Yes

SECF123 FlexCAN 8/28/08 Yes Yes Yes

SECF124 Cache 2/17/09 Yes Yes Yes

SECF125 FlexCAN 4/25/09 Yes Yes Yes

SECF036A PLL 6/9/10 Yes Yes Yes

SECF015 Flash 11/18/2014 Yes Yes Yes

The table below provides a revision history for this document.

Table 2. Document Revision History

Rev. No. Date Substantive Changes

3 5/2007 Added errata: SECF037 “Phase

Relationship Between CLKOUT and

CLKIN Not Preserved When Using PLL”

and SECF006 “FEC Duplicate

Transmission Bug”

4 8/2008 Added errata: SECF123 “FlexCAN

Writing to an Active Receive MB May

Corrupt MB Contents"

5 2/2009 Added status headings for each errata.

Added errata: SECF124 “Buffered Write

May Be Executed Twice”

6 4/2009 Added errata: SECF125 “Any FlexCAN

MB access during RX or TX of an

extended ID""frame’s CRC and EOF

may cause unwanted message

reception”

7 6/2010 Added errata: SECF036A “PLL Does

Not Lock in Normal PLL Mode with

Crystal Reference"

8 02/2015 Added errata: SECF015 “Internal Flash

Address Qualification Incomplete"

MCF5282 Chip Errata, Rev 8, 02/2015

2 Freescale Semiconductor, Inc.

SECF035: Leakage Current on V

DDPLL

Errata type:

Silicon

Affects:

PLL

Description:

The device exhibits a 65mA leakage current on the V

DDPLL

supply, regardless of chip

configuration.

Workaround:

No workaround.

Fix plan:

Fixed in datecodes XX0324 and later.

SECF003: BDM Load of SR Does Not Enable Stack Pointer Exchange

Errata type:

Silicon

Affects:

BDM

Description:

The V2 core used in this device adds support for separate user and supervisor stack pointers.

The hardware implements an active stack pointer and an other_stack_pointer. Whenever the

operating mode of the processor changes (supervisor to user or user to supervisor), the

processor hardware exchanges the active SP and the other SP.

This exchange operation does not work when the processor mode is changed by a write to the

SR from the BDM port. The hardware in the processor core required to process the BDM

load_SR operation and enable the stack pointer exchange is missing.

The exchange works properly when the SR is changed through software.

Workaround:

Use software for any operations that require exchanging the stack pointers.

Fix plan:

Currently, there are no plans to fix this.

SECF002: Unexpected Pipeline Stall on EMAC Load/Store Accumulator Instruction

Errata type:

Silicon

Affects:

EMAC

Description:

An unexpected pipeline stall occurs for accumulator load and accumulator store instructions

that immediately follow a load accumulator or MAC instruction.

Specifically, the operand execution pipeline (OEP) experiences a 2T pipeline stall when a load/

store accumulator instruction enters the pipeline immediately after any load accumulator or

MAC instruction. The pipeline is supposed to stall only if there is a store accumulator

instruction immediately following a load or MAC instruction that updated the specified

accumulator.

A simple example can be created to expose this problem:

mac.l ra,rb,acc0

mac.l rc,rd,acc0

mov.l acc1,rx

In the above example, the store of

acc1 (mov.l acc1,rx)

MCF5282 Chip Errata, Rev 8, 02/2015

Freescale Semiconductor, Inc. 3

P1-P3 P4-P6 P7-P9 P10-P12 P13-P13

MCF5281CVM80

Mfr. #:

Buy MCF5281CVM80

Manufacturer:

NXP / Freescale

Description:

32-bit Microcontrollers - MCU MCF5281 V2CORE 256KFLASH

Lifecycle:

New from this manufacturer.

Delivery:

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MCF5281CVM80

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