MCF5281CVM80 Datasheet MCF5281CVM80, MCF5281CVM66, MCF5282CVM66 | P4-P6

should not experience any stall because that accumulator is not being updated. In the current

V2 + EMAC implementation, it incorrectly stalls for two cycles.

NOTE

The operation of the instructions is correct. The problem is that the

expected timing is not met.

Workaround:

No workaround.

Fix plan:

Fixed in datecodes XXX0327 and later.

SECF021: Incorrect Cache Size

Errata type:

Silicon

Affects:

Cache

Description:

The device operates as if it were connected to an 8KB cache; however, the cache size is 2KB.

After the 2KB cache is full, the cache controller can have erroneous hits in the cache space

resulting in data and/or instruction corruption.

Workaround:

Do not enable the cache.

Fix plan:

Fixed in datecodes XXX0327 and later.

SECF004: Corrupted Fetches from Flash

Errata type:

Silicon

Affects:

Flash controller

Description:

Leaving bit 6 in the FLASHBAR register cleared can cause corrupted fetches from the device's

internal flash. For datecodes after XXX0327, the bit is hardwired high to prevent the corrupted

accesses.

Workaround:

Set bit 6 in the FLASHBAR. This prevents the corrupted fetches.

Fix plan:

Fixed in datecodes XXX0327 and later.

SECF005: Possible Cache Corruption After Clearing Cache (Setting CACR[CINV])

Errata type:

Silicon

Affects:

Version 2 ColdFire Cache

Description:

The cache on the V2 ColdFire core may function as either:

•

a unified data and instruction cache

• an instruction cache

• a data cache

The cache function and organization is controlled by the cache control register (CACR). The

CACR[CINV] bit causes a cache clear. If the cache is configured as a unified cache and the

CINV bit is set, the scope of the cache clear is controlled by two other bits in the CACR:

• CACR[INVI] invalidates instruction cache only

• CACR[INVD] invalidates data cache only

MCF5282 Chip Errata, Rev 8, 02/2015

4 Freescale Semiconductor, Inc.

If a write to the CACR is performed to clear the cache (CACR[CINV] = 1) and only a partial

clear is done (CACR[INVI] or CACR[INVD] set), then cache corruption may occur.

Workaround:

All loads of the CACR that perform a cache clear operation (CACR[CINV] set) should be

followed immediately by a NOP instruction. This avoids the cache corruption problem.

Fix plan:

Currently, there are no plans to fix this.

SECF001: Incorrect Operation of Cache Freeze (CACR[CFRZ])

Errata type:

Silicon

Affects:

Version 2 ColdFire Cache

Description:

The cache on the V2 ColdFire core is controlled by the cache control register (CACR). When

the CACR[CFRZ] bit is set, the cache freeze function is enabled and no valid cache array entry

is displaced. However, this feature does not always work as specified, sometimes allowing

valid lines to be displaced when CACR[CFRZ] is enabled.

This does not cause any corrupted accesses. However, there could be cache misses for data

that was originally loaded into the cache but was subsequently deallocated, even though the

CACR[CFRZ] bit was set.

Also, incoherent cache states are possible when a frozen cache is cleared via the

CACR[CINV] bit.

Workaround:

Unfreeze the cache by clearing CACR[CFRZ] when invalidating the cache using the

CACR[CINV] bit

Workaround:

Use the internal SRAM to store critical code/data if the system cannot handle a potential cache

miss

Fix plan:

Currently, there are no plans to fix this.

SECF029: Incorrect 32-bit Accesses to FlexCAN Registers

Errata type:

Silicon

Affects:

FlexCAN

Description:

Because the FlexCAN was originally designed for 16-bit architectures, all 32-bit register

accesses are broken down into two back-to-back 16-bit accesses. However, the timing for the

back-to-back accesses is incorrect and leads to corruption of the second 16-bit read or write.

Workaround:

When reading or writing to the 32-bit RxMASK registers, use two 16-bit accesses instead of a

single 32-bit access.

Fix plan:

Currently, there are no plans to fix this.

SECF009: FEC Receive Buffer Overrun in 10BaseT Mode

Errata type:

Silicon

Affects:

FEC

Description:

When the FEC is connected to a 10BaseT network, if length of the data stored in a descriptor

is not evenly divisible by 16 (not line-aligned), the FEC writes extra lines at the end of the

buffer. The entire line that contains the last valid data is written and at least one extra line, but

MCF5282 Chip Errata, Rev 8, 02/2015

Freescale Semiconductor, Inc. 5

up to four lines after the end of the valid data can also be written. In most cases, this is not a

problem because the extra lines of data continue falling within the limits of the buffer. However,

if the valid data ends near the end of the buffer, the extra lines written by the FEC might be

outside of the data buffer. This leads to corruption of the next buffer, descriptor, data, or code

stored in the adjacent memory.

For example, as shown in the figure below, if the max buffer size is programmed to 0x600 and

a frame that is 0x5F8 bytes long is received, a line is written starting at buffer start + 0x5F0.

The first half of the line at buffer start + 0x5F0 is valid frame data that should be processed by

the FEC driver; the second half of the line is additional data that is written because the FEC

only writes complete lines. This data should be ignored by the FEC driver. So far, this is

correct FEC behavior as originally specified. However, the FEC repeats the last line of valid

data a number of times. The line at buffer start + 0x600 is written, and as many as three

additional lines beyond the end of the data buffer could be written.

buffer start + 0x5E0

uffer start + 0x5F0

buffer start + 0x600

buffer start + 0x610

buffer start + 0x620

buffer start + 0x630

End of data buffer

Valid frame data

Expected extra data

Unexpected data/

verflows the data buffer

Figure 1. Buffer Overrun Example

Workaround:

Only use 100BaseT.

Workaround:

Allocate extra lines for the receive data buffers. The actual allocated memory for each buffer

should be equal to the receive buffer size programmed in the FEC’s EMRBR register plus four

lines (16 byte-sized lines).

Workaround:

Program the data buffer size one line larger than the max packet size (data buffer size =

EMRBR + 0x40).

Fix plan:

Currently, there are no plans to fix this.

SECF007: Concatenation of Received Frames in 10BaseT Mode

Errata type:

Silicon

Affects:

FEC

Description:

When the FEC is connected to a 10BaseT network, sometimes the FEC combines the data

from multiple frames to generate a single frame. The data from the frames is received

correctly, but the frame boundary is not reported correctly. This causes the descriptor to report

the length as the data length for all of the concantenated frames added together. The incorrect

data length might exceed the max frame length programmed in the RCR[MAX_FL] field.

MCF5282 Chip Errata, Rev 8, 02/2015

6 Freescale Semiconductor, Inc.

P1-P3 P4-P6 P7-P9 P10-P12 P13-P13

MCF5281CVM80

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Manufacturer:

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Description:

32-bit Microcontrollers - MCU MCF5281 V2CORE 256KFLASH

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