Workaround:
Use bypass mode, by setting CLKMOD[1:0] to 00. The CLKOUT to CLKIN phase relationship
is maintained.
Fix plan:
Currently, there are no plans to fix this.
SECF006: FEC Duplicate Transmission
Errata type:
Silicon
Affects:
FEC
Description:
In some cases, the FEC transmits single frames more than once. The FEC fetches transmit
buffer descriptors (TxBDs) and the corresponding Tx data continuously until the Tx FIFO is full.
It does not determine whether the TxBD to be fetched is already being processed internally (as
a result of a wrap). As the FEC nears the end of the transmission of one frame, it begins to
DMA the data for the next frame. To remain one BD ahead of the DMA, it also fetches the
TxBD for the next frame. It is possible that the FEC fetches from memory a BD that has
already been processed but not yet written back (it is read a second time with the R bit set). In
this case, the data is fetched and transmitted again.
Workaround:
Using at least three TxBDs fixes this problem for large frames, but not for small frames. To
ensure correct operation for large or small frames, one of the following must be true:
•
The FEC software driver ensures that there is always at least one TxBD with the Ready
bit cleared.
• Every frame uses more than one TxBD and every TxBD, but the last is written back
immediately after the data is fetched.
The FEC software driver ensures a minimum frame size, n. The minimum number of TxBDs is
then rounded up to the nearest integer (though the result cannot be less than 3). The default
Tx FIFO size is 192 Bytes; this size is programmable.
Fix plan:
Currently, there are no plans to fix this.
SECF123: FlexCAN Writing to an Active Receive MB May Corrupt MB Contents
Errata type:
Silicon
Affects:
FlexCAN
Description:
Deactivating a FlexCAN receive message buffer (MB) may cause corruption of another active
receive MB, including the ID field, if the following sequence occurs.
1.
A receive MB is locked via reading the control/status word, and has a pending frame in
the temporary receive serial message buffer (SMB).
2. A second frame is received that matches a second receive MB, and is queued in the
second SMB.
3. The first MB is unlocked during the time between receiving the CRC field and the sixth bit
of end of frame (EOF) of the second frame.
4. The second MB is deactivated within nine bus clock cycles of the sixth bit of EOF,
resulting in corruption of the first MB.
During standard use of the FlexCAN hardware, the errata can appear during heavy
communications with several Rx MBs at a low baudrate and while using Rx extended MB’s
IDs. This can be easily observed by checking ID value overwrite. In all cases, CAN
transmissions from the processor are not affected at any moment.
MCF5282 Chip Errata, Rev 8, 02/2015
Freescale Semiconductor, Inc. 9
