ROM FUNCTION COMMAND CODE DESCRIPTION
Search ROM F0h Search for a device
Read ROM 33h Read ROM from device (single drop)
Match ROM 55h Select a device by ROM number
Skip ROM CCh Select only device on 1-Wire
Resume A5h Selected device with RC bit set
Overdrive Skip ROM 3Ch Put all devices in overdrive
Overdrive Match ROM 69h Put the device with the ROM in overdrive
Table 1. 1-Wire ROM Commands Summary
Figure 7. ROM Function Flow, Part 2
69
h
OVERDRIVE
-
MATCH ROM
?
TO DEVICE FUNCTIONS
FLOW CHART
N
Y
A
5
h
RESUME
COMMAND?
3Ch
OVERDRIVE
-
SKIP ROM
?
N
N
RC =
0;
OD
=
1
MASTER Tx BIT
0
MASTER Tx BIT
1
Y Y Y
N
SLAVE Tx BIT 63
RC =
1
BIT 63
MATCH?
BIT 1 MATCH
?
BIT
0
MATCH?
MASTER Tx
RESET?
RC
=
1?
MASTER Tx
RESET?
Y
N
Y
N
RC
=
0;
OD =
1
OD =
0
N
OD = 0
N
OD =
0
N
Y
TO ROM FUNCTION FLOW PART 1
FROM ROM
FUNCTION
FLOW PART
1
FROM ROM FUNCTION
FLOW PART 1
TO ROM FUNCTION FLOW PART 1
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DS28E38 DeepCover® Secure ECDSA Authenticator
with ChipDNA PUF Protection
Search ROM[F0h]
When a system is initially brought up, the bus master
might not know the number of devices on the 1-Wire bus
or their ROM ID numbers. By taking advantage of the
wired-AND property of the bus, the master can use a pro-
cess of elimination to identify the ID of all slave devices.
For each bit in the ID number, starting with the least sig-
nificant bit, the bus master issues a triplet of time slots.
On the first slot, each slave device participating in the
search outputs the true value of its ID number bit. On the
second slot, each slave device participating in the search
outputs the complemented value of its ID number bit. On
the third slot, the master writes the true value of the bit
to be selected. All slave devices that do not match the
bit written by the master stop participating in the search.
If both of the read bits are zero, the master knows that
slave devices exist with both states of the bit. By choos-
ing which state to write, the bus master branches in the
search tree. After one complete pass, the bus master
knows the ROM ID number of a single device. Additional
passes identify the ID numbers of the remaining devices.
Refer to Application Note 187: 1-Wire Search Algorithm
for a detailed discussion, including an example.
Read ROM[33h]
The Read ROM command allows the bus master to read
the DS28E38’s 8-bit family code, unique 48-bit serial
number, and 8-bit CRC. This command can only be used
if there is a single slave on the bus. If more than one
slave is present on the bus, a data collision occurs when
all slaves try to transmit at the same time (open drain
produces a wired-AND result). The resultant family code
and 48-bit serial number result in a mismatch of the CRC.
Match ROM[55h]
The Match ROM command, followed by a 64-bit ROM
sequence, allows the bus master to address a specific
DS28E38 on a multidrop bus. Only the DS28E38 that
exactly matches the 64-bit ROM sequence responds
to the subsequent device function command. All other
slaves wait for a reset pulse. This command can be used
with a single device or multiple devices on the bus.
Skip ROM [CCh]
This command can save time in a single-drop bus system
by allowing the bus master to access the device functions
without providing the 64-bit ROM ID. If more than one
slave is present on the bus and, for example, a read com-
mand is issued following the Skip ROM command, data
collision occurs on the bus as multiple slaves transmit
simultaneously (open-drain pulldowns produce a wired-
AND result).
Resume [A5h]
To maximize the data throughput in a multidrop environ-
ment, the Resume command is available. This command
checks the status of the RC bit and, if it is set, directly
transfers control to the device function commands, similar
to a Skip ROM command. The only way to set the RC bit
is through successfully executing the Match ROM, Search
ROM, or Overdrive-Match ROM command. Once the RC
bit is set, the device can repeatedly be accessed through
the Resume command. Accessing another device on the
bus clears the RC bit, preventing two or more devices from
simultaneously responding to the Resume command.
Overdrive-Skip ROM [3Ch]
On a single-drop bus this command can save time by
allowing the bus master to access the device functions
without providing the 64-bit ROM ID. Unlike the normal
Skip ROM command, the Overdrive-Skip ROM command
sets the DS28E38 into the overdrive mode (OD = 1). All
communication following this command must occur at
overdrive speed until a reset pulse of minimum 480μs
duration resets all devices on the bus to standard speed
(OD = 0).
When issued on a multidrop bus, this command sets all
overdrive-supporting devices into overdrive mode. To
subsequently address a specific overdrive-supporting
device, a reset pulse at overdrive speed must be issued
followed by a Match ROM or Search ROM command
sequence. This speeds up the time for the search pro-
cess. If more than one slave supporting overdrive is pres-
ent on the bus and the Overdrive-Skip ROM command
is followed by a read command, data collision occurs on
the bus as multiple slaves transmit simultaneously (open-
drain pulldowns produce a wired-AND result).
Overdrive-Match ROM [69h]
The Overdrive-Match ROM command followed by a 64-bit
ROM sequence transmitted at overdrive speed allows the
bus master to address a specific DS28E38 on a multi-
drop bus and to simultaneously set it in overdrive mode.
Only the DS28E38 that exactly matches the 64-bit ROM
sequence responds to the subsequent device function
command. Slaves already in overdrive mode from a previ-
ous Overdrive-Skip ROM or successful Overdrive-Match
ROM command remain in overdrive mode. All overdrive-
capable slaves return to standard speed at the next reset
pulse of minimum 480μs duration. The Overdrive-Match
ROM command can be used with a single device or mul-
tiple devices on the bus.
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DS28E38 DeepCover® Secure ECDSA Authenticator
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Improved Network Behavior
(Switch-Point Hysteresis)
In a 1-Wire environment, line termination is possible only
during transients controlled by the bus master (1-Wire
driver). 1-Wire networks, therefore, are susceptible to
noise of various origins. Depending on the physical size
and topology of the network, reflections from end points
and branch points can add up or cancel each other to
some extent. Such reflections are visible as glitches or
ringing on the 1-Wire communication line. Noise coupled
onto the 1-Wire line from external sources can also result
in signal glitching. A glitch during the rising edge of a time
slot can cause a slave device to lose synchronization with
the master and, consequently, result in a Search ROM
command coming to a dead end or cause a device-spe-
cific function command to abort. For better performance
in network applications, the DS28E38 uses a 1-Wire front
end that is less sensitive to noise.
The DS28E38’s 1-Wire front-end has the following features:
There is additional lowpass filtering in the circuit that
detects the falling edge at the beginning of a time
slot. This reduces the sensitivity to high-frequency
noise. This additional filtering does not apply at over-
drive speed.
There is a hysteresis at the low-to-high switching
threshold V
TH
. If a negative glitch crosses V
TH
, but
does not go below V
TH
- V
HY
, it is not recognized
(Figure 8, Case A). The hysteresis is effective at any
1-Wire speed.
There is a time window specified by the rising edge
hold-off time t
REH
during which glitches are ignored,
even if they extend below the V
TH
- V
HY
threshold
(Figure 8, Case B, t
GL
< t
REH
). Deep voltage drops
or glitches that appear late after crossing the V
TH
threshold and extend beyond the t
REH
window can-
not be filtered out and are taken as the beginning of
a new time slot (Figure 8, Case C, t
GL
t
REH
).
PART TEMP RANGE PIN-PACKAGE
DS28E38Q+T -40°C to +85°C 6 TDFN (2.5k pcs)
+Denotes a lead(Pb)-free/RoHS-compliant package.
T = Tape and reel.
Figure 8. Noise Suppression Scheme
V
PUP
V
TH
V
HY
t
REH
t
GL
t
REH
t
GL
0V
CASE A CASE B CASE C
Ordering Information
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Maxim Integrated
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DS28E38 DeepCover® Secure ECDSA Authenticator
with ChipDNA PUF Protection

DS28E38Q+U

Mfr. #:
Manufacturer:
Maxim Integrated
Description:
Security ICs / Authentication ICs PUF ECDSA SECURE AUTHENTICATOR
Lifecycle:
New from this manufacturer.
Delivery:
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