(Limits are 100% tested at T
A
= +25°C and T
A
= +85°C. Limits over the operating temperature range and relevant supply voltage
range are guaranteed by design and characterization. Specifications marked GBD are guaranteed by design and not production tested.
Specifications to the minimum operating temperature are guaranteed by design and are not production tested. )
Note 1: System requirement. Maximum allowable pullup resistance is a function of the number of 1-Wire devices in the system
and 1-Wire recovery times. The specified value here applies to systems with only one device and with the minimum 1-Wire
recovery times.
Note 2: Value represents the typical parasite capacitance when V
PUP
is first applied. Once the parasite capacitance is charged,
it does not affect normal communication. Typically, during normal communication, the parasite capacitance is effectively
~100pF.
Note 3: V
TL
, V
TH
, and V
HY
are a function of the internal supply voltage, which is a function of V
PUP
, R
PUP
, 1-Wire timing, and
capacitive loading on IO. Lower V
PUP
, higher R
PUP
, shorter t
REC
, and heavier capacitive loading all lead to lower values of
V
TL
, V
TH
, and V
HY
.
Note 4: Voltage below which, during a falling edge on IO, a logic-zero is detected.
Note 5: The voltage on IO must be less than or equal to V
ILMAX
at all times the master is driving IO to a logic-zero level.
Note 6: Voltage above which, during a rising edge on IO, a logic-one is detected.
Note 7: After V
TH
is crossed during a rising edge on IO, the voltage on IO must drop by at least V
HY
to be detected as logic-zero.
Note 8: The I-V characteristic is linear for voltages less than 1V.
Note 9: System requirement. Applies to a single device attached to a 1-Wire line.
Note 10: The earliest recognition of a negative edge is possible at t
REH
after V
TH
has been previously reached.
Note 11: Defines maximum possible bit rate. Equal to 1/(t
W0LMIN
+ t
RECMIN
).
Note 12: System requirement. Interval after t
RSTL
during which a bus master can read a logic 0 on IO if there is a DS28E38 present.
The power-up presence detect pulse could be outside this interval but will be complete within 2ms after power-up.
Note 13: System requirement. ε in Figure 5 represents the time required for the pullup circuitry to pull the voltage on IO up from V
IL
to
V
TH
. The actual maximum duration for the master to pull the line low is t
W1LMAX
+ t
F
- ε and t
W0LMAX
+ t
F
- ε, respectively.
Note 14: System requirement. δ in Figure 5 represents the time required for the pullup circuitry to pull the voltage on IO up from V
IL
to
the input-high threshold of the bus master. The actual maximum duration for the master to pull the line low is t
RLMAX
+ t
F
.
Note 15: Current drawn from IO during a SPU operation interval. The pullup circuit on IO during the SPU operation interval should
be such that the voltage at IO is greater than or equal to V
SPUMIN
. A low-impedance bypass of R
PUP
activated during the
SPU operation is the recommended way to meet this requirement.
Note 16: Write-cycle endurance is tested in compliance with JESD47G.
Note 17: Not 100% production tested; guaranteed by reliability monitor sampling.
Note 18: Data retention is tested in compliance with JESD47G.
Note 19: Guaranteed by 100% production test at elevated temperature for a shorter time; equivalence of this production test to the
data sheet limit at operating temperature range is established by reliability testing.
Note 20: EEPROM writes can become nonfunctional after the data-retention time is exceeded. Long-term storage at elevated
temperatures is not recommended.
Note 21: An additional reset or communication sequence cannot begin until the reset high time has expired.
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Generate ECDSA
Signature
t
GES
130 ms
TRNG On-Demand
Check
t
ODC
20 ms
EEPROM
Write/Erase Cycles
(Endurance)
N
CY
(Notes 16, 17) 100K
Data Retention t
DR
T
A
= +85ºC (Notes 18, 19, 20) 10 years
Electrical Characteristics (continued)
www.maximintegrated.com
Maxim Integrated
│
5
DS28E38 DeepCover® Secure ECDSA Authenticator
with ChipDNA PUF Protection
