13
IDT72V3613 3.3V, CMOS CLOCKED FIFO WITH
BUS-MATCHING AND BYTE SWAPPING 64 x 36 COMMERCIAL TEMPERATURE RANGE
Figure 3. Logic Diagram for SIZ0, SIZ1, and BE Register
Figure 2. Dynamic Bus Sizing (Continued)
D
C
B35 B27 B26 B18 B17 B9 B8 B0
(d) BYTE SIZE
LITTLE-ENDIAN
1st: Read from FIFO
2nd: Read from FIFO
A
B
A35 A27 A26 A18 A17 A9 A8 A0
3rd: Read from FIFO
4th: Read from FIFO
BE SIZ1 SIZ0
H H L
4661 fig 01a
B35 B27 B26 B18 B17 B9 B8 B0
B35 B27 B26 B18 B17 B9 B8 B0
MUX
G1
1
1
D Q
SIZ0 Q
SIZ1 Q
BE
Q
SIZ0
SIZ1
BE
CLKB
4661 fig 02
14
IDT72V3613 3.3V, CMOS CLOCKED FIFO WITH
BUS-MATCHING AND BYTE SWAPPING 64 x 36 COMMERCIAL TEMPERATURE RANGE
Figure 4. Byte Swapping for FIFO Reads (Long-Word Size Example)
A35 A27 A26 A18 A17 A9 A8 A0
B35 B27 B26 B18 B17 B9 B8 B0
A
A
A
D
A
C
A
B
B
B
C
B
D
B
AB
C
C
C
B
C
A
C
D
D
D
D
A
D
B
D
C
(a) NO SWAP
(b) BYTE SWAP
(c) WORD SWAP
(d) BYTE-WORD SWAP
L L
SW1 SW0
SW1 SW0
SW1 SW0
SW1 SW0
L L
L H
H L
H H
4661 fi
g
03
A35 A27 A26 A18 A17 A9 A8 A0
B35 B27 B26 B18 B17 B9 B8 B0
A35 A27 A26 A18 A17 A9 A8 A0
B35 B27 B26 B18 B17 B9 B8 B0
A35 A27 A26 A18 A17 A9 A8 A0
B35 B27 B26 B18 B17 B9 B8 B0
15
IDT72V3613 3.3V, CMOS CLOCKED FIFO WITH
BUS-MATCHING AND BYTE SWAPPING 64 x 36 COMMERCIAL TEMPERATURE RANGE
Figure 5. FIFO Reset and Loading the X Register with the Value of Eight
Figure 6. Port A Write Cycle Timing
NOTE:
1. Written to the FIFO.
CLKA
RST
FF
AE
AF
MBF1,
MBF2
CLKB
EF
FS1,FS0
4661 drw 05
tRSTS
tRSTH
tFSH
tFSS
tWFF
tWFF
tPAE
0,1
tPAF
tRSF
tREF
t
ENS
CLKA
FF
ENA
MBA
CSA
W/RA
PEFA
A0 - A35
ODD/
EVEN
t
CLKH
t
CLKL
t
CLK
t
ENS
t
ENS
t
ENS
t
ENS
t
ENH
t
ENH
t
ENH
t
ENH
t
ENS
t
ENH
t
ENH
4661 drw 06
t
DS
t
DH
W1
W2
No Operation
ValidValid
t
PDPE
t
PDPE
HIGH
(1) (1)

72V3613L15PF

Mfr. #:
Manufacturer:
Description:
IC FIFO CLOCK 64X36 15NS 120TQFP
Lifecycle:
New from this manufacturer.
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