4
IDT72V3613 3.3V, CMOS CLOCKED FIFO WITH
BUS-MATCHING AND BYTE SWAPPING 64 x 36 COMMERCIAL TEMPERATURE RANGE
PIN DESCRIPTION (CONTINUED)
Symbol Name I/O Description
PEFB Port B Parity Error O When any valid byte applied to terminals B0-B35 fails parity, PEFB is LOW. Bytes are organized as
Flag (Port B) B0-B8, B9-B17, B-18-B26, and B27-B35, with the most significant bit of each byte serving as the parity
bit. A byte is valid when it is used by the bus size selected for port B. The type of parity checked is
determined by the state of the ODD/EVEN input.
The parity trees used to check the B0-B35 inputs are shared by the mail1 register to generate parity if
parity generation is selected by PGB. Therefore, if a mail1 read with parity generation is set up by having
CSB LOW, ENB HIGH, W/RB LOW, SIZ1 and SIZ0 HIGH and PGB HIGH, the PEFB flag is forced HIGH
regardless of the state of the B0-B35 inputs.
PGA Port A Parity I Parity is generated for data reads from the mail2 register when PGA is HIGH. The type of parity
Generation generated is selected by the state of the ODD/EVEN input. Bytes are organized at A0-A8, A9-A17, A18-
A26, and A27-A35. The generated parity bits are output in the most significant bit of each byte.
PGB Port B Parity I Parity is generated for data reads from port B when PGB is HIGH. The type of parity generated is
Generation selected by the state of the ODD/EVEN input. Bytes are organized as B0-B8, B9-B17, B18-B26, and
B27-B35. The generated parity bits are output in the most significant bit of each byte.
RST Reset I To reset the device, four LOW-to-HIGH transitions of CLKA and four LOW-to-HIGH transitions of CLKB
must occur while RST is LOW. This sets the AF, MBF1, and MBF2 flags HIGH and the EF, AE, and FF
flags LOW. The LOW-to-HIGH transition of RST latches the status of the FS1 and FS0 inputs to select
Almost-Full flag and Almost-Empty flag offset.
SIZ0, Port B Bus Size I A LOW-to-HIGH transition of CLKB latches the states of SIZ0, SIZ1, and BE, and the following LOW-to-
SIZ1 Selects (Port B) HIGH transition of CLKB implements the latched states as a port B bus size. Port B bus sizes can be long
word, word, or byte. A HIGH on both SIZ0 and SIZ1 chooses a mailbox register for a port B 36-bit write or
read.
SW0, Port B Byte Swap I At the beginning of each long word FIFO read, one of four modes of byte-order swapping is selected by
SW1 Selects (Port B) SW0 and SW1. The four modes are no swap, byte swap, word swap, and byte-word swap. Byte-order
swapping is possible with any bus-size selection.
W/RA Port A Write/Read I A HIGH selects a write operation and a LOW selects a read operation on port A for a LOW-to-HIGH
Select transition of CLKA. The A0-A35 outputs are in the high-impedance state when W/RA is HIGH.
W/RB Port B Write/Read I A HIGH selects a write operation and a LOW selects a read operation on port B for a LOW-to-HIGH
Select transition of CLKB. The B0-B35 outputs are in the high-impedance state when W/RB is HIGH.
