20
IDT72V3613 3.3V, CMOS CLOCKED FIFO WITH
BUS-MATCHING AND BYTE SWAPPING 64 x 36 COMMERCIAL TEMPERATURE RANGE
Figure 11.
FFFF
FFFF
FF
Flag Timing and First Available Write when the FIFO is Full
NOTES:
1. tSKEW1 is the minimum time between a rising CLKB edge and a rising CLKA edge for EF to transition HIGH in the next CLKA cycle. If the time between the rising CLKB edge and
rising CLKA edge is less than tSKEW1, then the transition of EF HIGH may occur one CLKA cycle later than shown.
2. Port B size of long word is selected for the FIFO read by SIZ1 = LOW, SIZ0 = LOW. If port B size is word or byte, tSKEW1 is referenced from the rising CLKB edge that reads the
last word or byte of the long word, respectively.
NOTES:
1. tSKEW2 is the minimum time between a rising CLKA edge and a rising CLKB edge for AE to transition HIGH in the next CLKB cycle. If the time between the rising CLKA edge and
rising CLKB edge is less than tSKEW2, then AE may transition HIGH one CLKB cycle later than shown.
2. FIFO write (CSA = LOW, W/RA = HIGH, MBA = LOW), FIFO read (CSB = LOW, W/RB = LOW, either SIZ0 = LOW or SIZ1 = LOW).
3. Port B size of long word is selected for the FIFO read by SIZ1 = LOW, SIZ0 = LOW. If port B size is word or byte, tSKEW2 is referenced to the last word or byte of the long word,
respectively.
Figure 12. Timing for
AEAE
AEAE
AE
when the FIFO is Almost-Empty
CSB
EF
W/RB
SIZ1,
SIZ0
ENB
B0 -B35
CLKB
FF
CLKA
CSA
WRA
A0 - A35
MBA
ENA
4661 drw 11
12
t
CLK
t
CLKH
t
CLKL
t
ENS
t
ENH
t
A
t
SKEW1
t
CLK
t
CLKH
t
CLKL
t
WFF
t
ENS
t
ENS
t
DS
t
ENH
t
ENH
t
DH
To FIFO
Previous Word in FIFO Output Register
Next Word From FIFO
LOW
LOW
LOW
HIGH
LOW
HIGH
(1)
FIFO Full
t
WFF
AE
CLKA
ENA
CLKB
ENB
4661 drw 12
2
1
tENS
tENH
tSKEW2
tPAE
tPAE
tENS
tENH
X Long Words in FIFO
(X+1) Long Words in FIFO
(1)
