MOTOROLA MPC565/MPC566 Product Brief 3
Detailed Feature List
1.2 Detailed Feature List
The MPC565 key features are explained in the following sections.
1.2.1 High Performance CPU System
• Fully static design
• Four major power saving modes
— On, doze, sleep, deep-sleep and power-down
1.2.2 RISC MCU Central Processing Unit (RCPU)
• High-performance core
— PowerPC single issue integer core
— Precise exception model
— Floating point
— Code compression (MPC566 only)
– Compression reduces usage of internal or external Flash memory
– Compression optimized for automotive (non-cached) applications
– New compression scheme decreases code size to 40% –50% of source
1.2.3 MPC500 System Interface (USIU)
• MPC500 system interface (USIU, BBC, L2U)
• Periodic interrupt timer, bus monitor, clocks, decrementer and time base
• Clock synthesizer, power management, reset controller
• External bus tolerates 5-V inputs, provides 2.6-V outputs
• Enhanced interrupt controller supports a separate interrupt vector for up to eight external and 40
internal interrupts
• IEEE 1149.1 JTAG test access port
• Bus supports multiple master designs
• USIU supports dual-mapping of Flash to move part of internal Flash memory to external bus for
development
• External bus, supporting non-wraparound burst for instruction fetches, with up to 8 instructions
per memory cycle
1.2.4 Burst Buffer Controller (BBC) Module
• Exception vector table relocation features allow exception table to be relocated to following
locations:
— 0x0000 0000 - 0x0000 1FFF (normal MPC500 exception table location)
— 0x0001 0000 - 0x0001 1FFF (0 + 64 Kbytes; second page of internal Flash)
— Second internal Flash module
— Internal SRAM
— 0x0FFF_0100 (external memory space; normal MPC500 exception table location)
Frees
cale Semiconductor,
I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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