MPC565CZP56 Datasheet MPC565MVR56, MPC565CZP56, MPC565CVR56 | P4-P6

4 MPC565/MPC566 Product Brief MOTOROLA

Detailed Feature List

1.2.5 Flexible Memory Protection Unit

• Flexible memory protection units in BBC (IMPU) and L2U (DMPU)

• Default attributes available in one global entry

• Attribute support for speculative accesses

1.2.6 Memory Controller

• Flexible chip selects via memory controller

• 24-bit address and 32-bit data buses

• 4- to 16-Mbyte (data) or 4-Gbyte (instruction) region size support

• Four-beat transfer bursts, two-clock minimum bus transactions

• Use with SRAM, EPROM, Flash and other peripherals

• Byte selects or write enables

• 32-bit address decodes with bit masks

• Four instruction regions

• Four data regions

1.2.7 1 Mbyte of CDR3 Flash EEPROM Memory (UC3F)

•1 Mbyte Flash

— Two UC3F modules, 512 Kbytes each

• Page mode read

• Block (64-Kbyte) erasable

• External 4.75- to 5.25-V VPP program and erase power supply

• Typical endurance of 100,000 write/erase cycles @ 25ºC

• Typical data retention of 100 years @ 25ºC

1.2.8 36-Kbyte Static RAM (CALRAM)

• 36-Kbyte static calibration RAM

— Composed of 4-Kbyte and 32-Kbyte CALRAM modules

• Fast access: one clock

• Keep-alive power

• Soft defect detection (SDD)

• 4 Kbyte calibration (overlay) RAM per module (8 Kbytes total)

• Eight 512-byte overlay regions per module (16 regions total)

1.2.9 General Purpose I/O Support (GPIO)

• General-purpose I/O support

• Address (24) and data (32) pins can be used as GPIO in single-chip mode

• 16 GPIO in MIOS14

• Many peripheral pins can be used as GPIO when not used as primary functions

• 5-V outputs with slew rate control

Frees

cale Semiconductor,

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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MOTOROLA MPC565/MPC566 Product Brief 5

Detailed Feature List

1.2.10 Debug Features

• Extensive system debug support

• On-chip watchpoints and breakpoints

• Program flow tracking

• Background debug mode (BDM)

1.2.10.1 Nexus Debug Port (Class 3)

• Nexus/IEEE – ISTO 5001-1999 debug port (Class 3)

• Nine- or 16-pin interface

1.2.10.2 Message Data Link Controller (DLCMD2) Module

• Two pins muxed with QSMCMB pins. Muxing controlled by QSMCMB PCS3 pin assignment

• SAE J1850 Class B data communications network interface compatible and ISO compatible for

low-speed (

<125 Kbps) serial data communications in automotive applications

• 10.4 Kbps variable pulse width (VPW) bit format

• Digital noise filter, collision detection

• Hardware cyclical redundancy check (CRC) generation and checking

• Block mode receive and transmit supported

• 4x receive mode supported (41.6 Kbps)

• Digital loopback mode

• In-frame response (IFR) types 0, 1, 2, and 3 supported

• Dedicated register for symbol timing adjustments

• Inter-module bus 3 (IMB3) slave interface

• Power-saving IMB3 stop mode with automatic wakeup on network activity

• Power-saving IMB3 CLOCKDIS mode

• Debug mode available through IMB3 FREEZE signal or user controllable SOFT_FRZ bit

• Polling and IMB3 interrupt generation with vector lookup available

1.2.11 Integrated I/O System

• True 5-V I/O

1.2.11.1 Time Processor Units (TPU3)

• Three time processing units (TPU3)

— 16 channels each

• Each TPU3 is a microcoded timer subsystem

• One 6-Kbyte and one 4-Kbyte dual-port TPU RAM (DPTRAM), one (6-Kbyte) shared by two

TPU3 modules for TPU microcode and the 4-Kbyte dedicated to the third TPU3 for microcode.

Frees

cale Semiconductor,

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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6 MPC565/MPC566 Product Brief MOTOROLA

Detailed Feature List

1.2.11.2 22-Channel Modular I/O System (MIOS14)

• 22-channel MIOS timer (MIOS14)

• Six modulus counter submodules (MCSM)

— Four additional MCSM submodules compared to MIOS1

• 10 double action submodules (DASM).

• 12 dedicated PWM submodules (PWMSM)

— Four additional PWM submodules compared to MIOS1 (shared with MIOS GPIO pins)

• MIOS real-time clock submodule (MRTCSM) provides low power clock/counter

— Requires external 32-KHz crystal

— Uses four pins: two for 32-KHz crystal, two for power/ground.

1.2.12 Two Enhanced Queued Analog-to-Digital Converter

Modules (QADC64E)

• Two enhanced queued analog to digital converters (QADC64E A, QADC64E B) with AMUXes

for 40 total analog channels.

• 10 bit A/D converter with internal sample/hold

— Typical conversion time is 4 µs (250-Kbyte samples/sec)

— Two conversion command queues of variable length

• Automated queue modes initiated by:

— External edge trigger/level gate

— Software command

— Periodic/interval timer, assignable to both queue 1 and 2

• 64 result registers in each QADC64E module

— Output data is right or left justified, signed or unsigned

• Synchronized clock mode allows both QADC64Es to see the same conversion clock. This allows

the two modules to look like one large QADC with four queues.

• Conversions alternate reference (ALTREF) pin. This pin can be connected to a different reference

voltage

1.2.13 Three CAN 2.0B Controller (TouCAN) Modules

• Three TouCAN modules (TouCAN_A, TouCAN_B, and TouCAN_C)

• 16 message buffers each, programmable I/O modes

• Maskable interrupts

• Programmable loopback for self-test operation

• Independent of the transmission medium (external transceiver is assumed)

• Open network architecture, multimaster concept

• High immunity to EMI

• Short latency time for high-priority messages

• Low power sleep mode, with programmable wake up on bus activity

• TouCAN_C pins shared with MIOS14 GPIO pins

Frees

cale Semiconductor,

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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MPC565CZP56

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32-bit Microcontrollers - MCU MPC565 1024KFLASH Qorivva

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