MPC565CZP56 Datasheet MPC565MVR56, MPC565CZP56, MPC565CVR56 | P7-P9

MOTOROLA MPC565/MPC566 Product Brief 7

Detailed Feature List

1.2.14 Queued Serial Multi-Channel Modules (QSMCM)

• Two queued serial modules with one queued-SPI and two SCI each (QSMCM_A, QSMCM_B)

— QSMCM_A matches full MPC555 QSMCM functionality

— QSMCM_B has pins muxed with DLCMD2 module

– Two pins are muxed with DLCMD2 (J1850) transmit and receive pins

(B_PCS3_J1850_TX and B_RXD2_J1850_RX)

– QSMCM B vs J1850 mux control provided by QPAPCS3 bit in QSMCM pin assignment

• Queued-SPI

— Provides full-duplex communication port for peripheral expansion or interprocessor

communication

— Up to 32 preprogrammed transfers, reducing overhead

— Synchronous serial interface with baud rate of up to system clock / 4

— Four programmable peripheral-select pins support up to 16 devices

— Special wrap-around mode allows continuous sampling of a serial peripheral for efficient

interfacing to serial analog-to-digital (A/D) converters

•SCI

— UART mode provides NRZ format and half- or full-duplex interface

— 16 register receive buffer and 16 register transmit buffer on one SCI

— Advanced error detection, and optional parity generation and detection

— Word length programmable as 8 or 9 bits

— Separate transmitter and receiver enable bits, and double buffering of data

— Wake-up functions allow the CPU to run uninterrupted until either a true idle line is detected,

or a new address byte is received

1.2.15 Electrical Specifications and Packaging

• 40 MHz operation (56 MHz operation is optional for the MPC566)

•-40

°C – 125°C ambient temperature, -40°C – 85°C for suffix C device, -55°C– 125°C for suffix A

devices

•2.6 V

± 0.1 V external bus

— External bus is compatible with external memory devices operating from 2.5 V to 3.4 V.

— Extended voltage range (2.7 – 3.4 V) degrades data drive timing by 1.1 ns on date writes.

•2.6

± 0.1 V internal logic

• 5-V I/O (5.0

± 0.25 V)

• Available in package or bumped die

• Plastic ball grid array (PBGA) packaging

– 388 ball PBGA

– 27 mm x 27 mm body size

• 1.0 mm ball pitch

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cale Semiconductor,

Freescale Semiconductor, Inc.

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Go to: www.freescale.com

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8 MPC565/MPC566 Product Brief MOTOROLA

MPC565 Optional Features

1.3 MPC565 Optional Features

The following features of the MPC565 are optional features and may not appear in certain configurations:

• 56-MHz operation (40-MHz is default)

• MPC566 supports code compression

2 Differences between the MPC565 and the MPC555

The MPC565 is an enhanced version of the MPC555. Most functional features of the MPC555 are

unchanged on the MPC565. Table 2 shows the high level differences.

Table 2. Differences Between Modules of the MPC555 and the MPC565

Module MPC555 MPC565

CPU Core No Change

BBC BBC BBC with improved code compression

Available on some options.

L2U No Change

SRAM 26-Kbytes 36-Kbyte CALRAM with overlay features

Flash 448-Kbyte CMF 1-Mbyte UC3F

(new programming, etc.)

USIU USIU USIU with enhanced interrupt controller

JTAG No Change

READI None New Module

UIMB No Change

QADC64 2 QADC64 (16 channels on each QADC

for 32 total channels)

2 QADC64E w/AMUXes

(

40 channels accessible from either

QADC64E)

QSMCM (1) No Change (2)

DLCMD2 (J1850) None 1

MIOS MIOS1 MIOS14: MIOS1 with real-time clock

(MRTCSM), 4 more PWMSMs and 4 more

MCSMs

TouCAN (2) No Change (3)

TPU3 (2) No Change (3)

DPTRAM (6-Kbytes) No Change (6-Kbytes, 4-Kbytes)

Power Supplies

— 40 MHz with two power supplies:

nominal 3.3-V to 5.0-V power supplies

56 MHz with two power supplies:

5.0-V I/O, 2.6-V internal logic

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cale Semiconductor,

Freescale Semiconductor, Inc.

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MOTOROLA MPC565/MPC566 Product Brief 9

Additional MPC565 Differences

2.1 Additional MPC565 Differences

The following are additional differences between the MPC555 and the MPC565.

• SPI (MISO, MOSI, and SCK) pin drive.

— MPC565 provides 21-ns rise/fall with 200-pf load using CMOS (20%/70%) levels

• GPIO on MODCK1 pin outputs only 2.6 V

— MODCK1 pin is in keep-alive power section with no 5-V rail available

— 5.0-V compatibility modes

– Input is 5-V friendly

– 2.6-V output has less slew rate control

– 2.6-V: VOH = 2.3 V

• Power supplies for external bus pins

— QVDDL is quiet supply to hold non-switching outputs quiet even when noisy supply

(NVDDL) sags

— QVDDL supplies pre-drive and other pad logic

— NVDDL only supplies final PMOS driver stage

— QVDDL and NVDDL shorted on customer board after filtering

• Pull-up and pull-down changes during PORESET and HRESET

— All 2.6-V/5-V pads (external bus: address/data/control) pull down at reset

— All 5-V pads pull up at reset

— Additional control granularity in the PDMCR register

• No pull-ups on QSMCM SCI receive pads

• A_RXD1_QGPI1, A_RXD2_QGPI2, B_RXD1_QGPI1 pins do not have weak pull-up during

reset or any other time

• CLKOUT has 3 drive strength options

— Better matches drive to requirements to reduce EMI

— 25, 50, 100 pf instead of 45 and 90 pf

• Change reset value of ENGCLK to maximum divide (crystal/128)

— For a 4-MHz crystal, this is 31.25 KHz

– ENGCLK is selectable between 2.6 V and 5 V

• A daisy chain between UC3F modules allows either module to provide the reset configuration

word (RCW)

• Censorship operation

— A RCW bit controls whether or not the entire UC3F can be erased while censorship is violated

• BBC SPRs (PPC regs) access in two clocks instead of one clock

• CALRAM internal protection block size is 8 Kbytes

— Instead of 4 Kbytes on MPC555 LRAM

• CALRAM causes machine check exception instead of data storage interrupt (DSI) exception in

certain cases

— For non-overlay CPU core accesses, a DSI exception is taken

— For overlay accesses and any non-core access (slave mode), a machine check exception is

taken

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cale Semiconductor,

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MPC565CZP56

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